Patents by Inventor Nitin Agarwal

Nitin Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200395921
    Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 17, 2020
    Inventors: Aniruddha ROY, Nitin AGARWAL, Rajavelu THINAKARAN
  • Publication number: 20200387891
    Abstract: A method for facilitating the exchange of a stable cryptocurrency collateralized by government-issued debt. First granularity parameters are received through a first wallet interface of a first digital wallet. A first restricted use key is generated based upon the first granularity parameters and provided to an owner of a second digital wallet. A second restricted use key is generated based upon second granularity parameters received through a second wallet interface associated with the second digital wallet. Information from a blockchain wallet is accessed using the second restricted use key wherein the information relates to one or more of an ID classification and risk score of the second wallet owner at a level of detail determined by the second granularity parameters. An indication to proceed with a transaction between the first digital wallet and the second digital wallet may then be received through the first wallet interface.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 10, 2020
    Inventors: Miles PASCHINI, Nitin AGARWAL
  • Patent number: 10861639
    Abstract: A device for controlling a switching mode power supply includes a regulation module, a feedback node, and a resistance module. The regulation module is adapted to cause a switching module to selectively couple, based on an oscillation frequency, a primary side winding of a transformer and a supply to control a voltage, current, or power output at a secondary side winding of the transformer. The feedback node is adapted to receive an indication of a voltage at the secondary side winding of the transformer. The resistance module is adapted to selectively set a pull-up resistance based on a comparison between a time-controlled frequency and a voltage-controlled frequency that is generated based on a voltage at the feedback node, wherein the regulation module is adapted to set the oscillation frequency as the time-controlled frequency or the voltage-controlled frequency.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 8, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Dong Li, Nitin Agarwal, Po-Jung Chung
  • Publication number: 20200343867
    Abstract: A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 29, 2020
    Inventors: Nitin AGARWAL, Aniruddha ROY
  • Publication number: 20200321932
    Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 8, 2020
    Inventors: Suresh MALLALA, Nitin AGARWAL
  • Publication number: 20200321952
    Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 8, 2020
    Inventors: Nitin Agarwal, Venkat Ramakrishna Saripalli, Venkata Ramanan R
  • Patent number: 10763832
    Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: September 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aniruddha Roy, Nitin Agarwal, Rajavelu Thinakaran
  • Publication number: 20200104846
    Abstract: A system and method for facilitating electronic commerce over a network, according to one or more embodiments, includes communicating with a user via a user device and an issuer of payment media via an issuer device over the network, the payment media being issued to the user by the issuer, receiving user instruction over the network to link the payment media to a user account related to the user, prompting the user over the network to input a secure password known only by the issuer and the user, receiving the secure password from the user over the network, verifying that the payment media is owned by the user over the network via a secure protocol, returning a response to the user related to verification of the payment media, and storing payment media verification information.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 2, 2020
    Inventors: Nitesh Singhal, Parijat Sinha, Nitin Agarwal, Muthukumar Murugesan
  • Publication number: 20200090859
    Abstract: A device for controlling a switching mode power supply includes a regulation module, a feedback node, and a resistance module. The regulation module is adapted to cause a switching module to selectively couple, based on an oscillation frequency, a primary side winding of a transformer and a supply to control a voltage, current, or power output at a secondary side winding of the transformer. The feedback node is adapted to receive an indication of a voltage at the secondary side winding of the transformer. The resistance module is adapted to selectively set a pull-up resistance based on a comparison between a time-controlled frequency and a voltage-controlled frequency that is generated based on a voltage at the feedback node, wherein the regulation module is adapted to set the oscillation frequency as the time-controlled frequency or the voltage-controlled frequency.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 19, 2020
    Inventors: Dong Li, Nitin Agarwal, Po-Jung Chung
  • Publication number: 20200089263
    Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.
    Type: Application
    Filed: November 20, 2019
    Publication date: March 19, 2020
    Inventors: Sachin Sudhir Turkewadikar, Nitin Agarwal, Madhan Radhakrishnan
  • Publication number: 20200057106
    Abstract: In one embodiment, a method of operating a computational system to evaluate a device under test, where the device under test is operable to receive a digital code input and output in response a corresponding output. The method injects a plurality of simulated faults into a pre-silicon model of the device under test. For each injected simulated fault, the method inputs a plurality of digital codes to the model. For each input digital code, the method selectively stores the input digital code if a difference, between a corresponding output for the input digital code and a no-fault output for the input, exceeds a predetermined threshold value.
    Type: Application
    Filed: August 12, 2019
    Publication date: February 20, 2020
    Inventors: Lakshmanan Balasubramanian, Nadeem Husain Tehsildar, Rubin Ajit Parekhji, Suresh Mallala, Nitin Agarwal
  • Patent number: 10534387
    Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: January 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sachin Sudhir Turkewadikar, Nitin Agarwal, Madhan Radhakrishnan
  • Publication number: 20190361475
    Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.
    Type: Application
    Filed: June 11, 2019
    Publication date: November 28, 2019
    Inventors: Nitin Agarwal, Rajavelu Thinakaran, Sumit Dubey
  • Patent number: 10443259
    Abstract: A pool cleaner including a turbine assembly, a timer assembly, and a scrubber assembly. The timer assembly is configured to rotate the turbine assembly in a first direction and a second direction. The scrubber assembly is configured to rotate in a forward direction when the turbine assembly rotates in the first direction, and to rotate in a rearward direction when the turbine assembly rotates in the second direction.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 15, 2019
    Assignee: Pentair Water Pool and Spa, Inc.
    Inventors: Suresh C. Gopalan, Nitin Agarwal, Jayamurali Kaladharan
  • Publication number: 20190199330
    Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Inventors: Aniruddha ROY, Nitin AGARWAL, Rajavelu THINAKARAN
  • Patent number: 10317925
    Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nitin Agarwal, Rajavelu Thinakaran, Sumit Dubey
  • Publication number: 20190123543
    Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Sumit Dubey, Nitin Agarwal
  • Publication number: 20190078346
    Abstract: A pool cleaner comprises a housing including at least two wheels, a supply mast, and a timer disc assembly configured to receive water from the supply mast. The timer disc assembly includes an outer housing, a plurality of outlet ports extending through the outer housing, and a rotating timer disc positioned within the outer housing adjacent to the plurality of outlet ports. The timer disc assembly also includes at least one stationary port seal liner positioned between one of the plurality of outlet ports and the rotating timer disc. The at least one stationary port seal liner includes an elastomeric piece and a liner piece, and the liner piece is in contact with the rotating timer disc.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 14, 2019
    Inventors: Suresh Gopalan, Nitin Agarwal, Jayamurali Kaladharan, Brian King, Leonard Richiuso
  • Patent number: 10211621
    Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: February 19, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Sumit Dubey, Nitin Agarwal
  • Publication number: 20180330725
    Abstract: A method for priming an extensible speech recognition system comprises receiving audio language input from a user. The method also comprises receiving an indication that the audio language input is associated with a first language-based intelligent agent. The first language-based intelligent agent is associated with a first grammar set that is specific to the first language-based intelligent agent. Additionally, the method comprises matching one or more spoken words or phrases within the audio language input to text-based words or phrases within a general grammar set associated with a speech recognition system and the first grammar set. The first grammar set is associated with a higher match bias than the general grammar set, such that the speech recognition system is more likely to match the one or more spoken words or phrases to the text-based words or phrases within the first grammar set.
    Type: Application
    Filed: August 18, 2017
    Publication date: November 15, 2018
    Inventors: Padma VARADHARAJAN, Shuangyu CHANG, Khuram SHAHID, Meryem Pinar DONMEZ EDIZ, Nitin AGARWAL