Patents by Inventor Nitin Gupta

Nitin Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210313802
    Abstract: Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.
    Type: Application
    Filed: June 16, 2021
    Publication date: October 7, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shiv Harit MATHUR, Nitin GUPTA
  • Publication number: 20210304564
    Abstract: In a gaming machine, a first display area displays a plurality of wager options. A wager selection mechanism is operable by a player to select more than one of the wager options to be activated concurrently and to individually select wager amounts to apply to each selected wager option. A second display area displays a game outcome of a spinning reel game of chance. A game outcome evaluator evaluates the game outcome based on each of the concurrently activated wager options and respective ones of the individually selected wager amounts.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Billy Tam, Nitin Gupta, Gaurav Goel, Pradip Rangari
  • Patent number: 11132500
    Abstract: One embodiment provides a method, including: receiving, from a client, (i) a task of annotating information, (ii) a set of instructions for performing the task, and (iii) client annotations for a subset of the information within the task; assigning the subset to a plurality of annotators; obtaining (i) annotator annotations for the subset and (ii) a response time for providing the annotator annotation for each piece of information within the subset; identifying improvements to the set of instructions by (i) comparing the annotator annotations to the client annotations and (ii) identifying discrepancies made by the annotators in view of the response time; and generating a new set of instructions, wherein the generating comprises (i) identifying at least one feature of the information that distinguishes correctly annotated information from incorrectly annotated information and (ii) generating an instruction from the at least one feature.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: September 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shashank Mujumdar, Nitin Gupta, Arvind Agarwal, Sameep Mehta
  • Publication number: 20210295036
    Abstract: One embodiment provides a method, including: receiving a technical diagram comprising a plurality of nodes and edges, wherein each edge connects two of the plurality of nodes; extracting, from the technical diagram, entities represented within the technical diagram, wherein the entities are extracted from the nodes and edges; creating groupings of entities from the extracted entities by grouping entities into groups based upon a logical relationship between the entities within a given group; generating, from the groupings, a visual representation of the technical diagram, wherein the visual representation comprises the groupings being represented as text and arranged based upon contextual relationships between the groupings; and providing a natural language summary of the technical diagram, wherein the providing comprises converting the visual representation into natural language text.
    Type: Application
    Filed: March 18, 2020
    Publication date: September 23, 2021
    Inventors: Prerna Agarwal, Nitin Gupta, Shashank Mujumdar, Arun Kumar
  • Patent number: 11098037
    Abstract: The present invention relates to a process for preparing the Alectinib or a pharmaceutically acceptable salt thereof using lesser reaction steps and also eliminating expensive and time-consuming column chromatography. The invention also relates to novel polymorphic forms of Alectinib and Alectinib hydrochloride.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: August 24, 2021
    Assignee: Fresenius Kabi Oncology Ltd.
    Inventors: Vinod Singh Tomar, Abul Azim, Nitin Gupta, Saswata Lahiri, Walter Cabri
  • Patent number: 11100123
    Abstract: One embodiment provides a method, including: receiving a plurality of data for job processing, wherein the job processing processes the plurality of data into (i) at least one map phase and (ii) at least one reduce phase; generating a plurality of key-value groups from the plurality of data, wherein the plurality of key-value groups are grouped from data pairs including a key and a value and wherein each of the key-value groups include a grouping of data pairs having a common key and a plurality of values associated with the common key; identifying values common to at least a subset of the key-value groups; generating, based upon the identifying, new key-value groups, wherein at least a subset of the new key-value groups includes key-value groups having common keys and the identified common values; and communicating the new key-value groups to the at least one reduce function for processing.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: August 24, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Himanshu Gupta, Nitin Gupta
  • Patent number: 11095297
    Abstract: A voltage controlled oscillator (VCO) circuit generates an output signal having a frequency which is dependent on a control voltage. A current is generated which is itself dependent on an amplitude of the VCO circuit. The generated current accordingly tracks, to an extent, the temperature behavior of the oscillator within the VCO circuit. The oscillator is driven by the sum of the generated current and a control current dependent on the control voltage. The control voltage may, for example, be generated by a phase lock loop (PLL).
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Sagnik Mukherjee
  • Patent number: 11093813
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for identifying answers to questions using neural networks. One of the methods includes receiving an input text passage and an input question string; processing the input text passage using an encoder neural network to generate a respective encoded representation for each passage token in the input text passage; at each time step: processing a decoder input using a decoder neural network to update the internal state of the decoder neural network; and processing the respective encoded representations and a preceding output of the decoder neural network using a matching vector neural network to generate a matching vector for the time step; and generating an answer score that indicates how well the input text passage answers a question posed by the input question string.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: August 17, 2021
    Assignee: GOOGLE LLC
    Inventors: Ni Lao, Lukasz Mieczyslaw Kaiser, Nitin Gupta, Afroz Mohiuddin, Preyas Popat
  • Patent number: 11079824
    Abstract: Systems and methods for power distribution are disclosed. A system includes a first power domain that supplies current to an integrated circuit at a first voltage level, a second power domain that supplies current to the integrated circuit at a second voltage level, and a current distribution component that is connected to the first power domain and connectable to the second power domain and senses a metric comprising a first current level or a first voltage level drawn from the first power domain, determines whether the metric exceeds a first threshold, and in response to determining that the metric exceeds the first threshold, electrically connects the second power domain to the integrated circuit to supply additional current such that an aggregate current level received by the integrated circuit comprises current from the first power domain and the additional current from the second power domain.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 3, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Nitin Gupta, Bhavin Odedara, Raghu Voleti
  • Patent number: 11062565
    Abstract: In a gaming machine, a first display area displays a plurality of wager options. A wager selection mechanism is operable by a player to select more than one of the wager options to be activated concurrently and to individually select wager amounts to apply to each selected wager option. A second display area displays a game outcome of a spinning reel game of chance. A game outcome evaluator evaluates the game outcome based on each of the concurrently activated wager options and respective ones of the individually selected wager amounts.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: July 13, 2021
    Assignee: Aristocrat Technologies Australia Pty Limited
    Inventors: Billy Tam, Nitin Gupta, Gaurav Goel, Pradip Rangari
  • Patent number: 11056880
    Abstract: Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 6, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shiv Harit Mathur, Nitin Gupta
  • Patent number: 11043488
    Abstract: Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: June 22, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Nitin Gupta, Ramakrishnan Subramanian, Sitaram Banda
  • Patent number: 11044248
    Abstract: A method is provided for facilitating mutual authenticating between a server and a user of a haptic enabled device. The method comprises providing identity information of a user to a server, and in response, providing a haptic feedback output to the user corresponding to the identity information. Further, the user compares the haptic feedback output received from the server to a haptic feedback pattern as predefined by the user, to determine whether the server is authenticated or not.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: June 22, 2021
    Assignee: Symbol Technologies, LLC
    Inventors: Nitin Gupta, Sundaresan Sundaram
  • Publication number: 20210185695
    Abstract: A method for feedback-based network slice management includes steps performed at a network slice management function (NSMF) including at least one processor. The steps include subscribing, via a network data analytics function (NWDAF) subscription interface of the NSMF, directly with the NWDAF to create a subscription to be notified of network slice load information and specifying, as part of the subscription, network slice load information report generation criteria defined by the NSMF. The steps further include receiving, directly from the NWDAF, via the NWDAF subscription interface of the NSMF and in response to the NSMF-defined network slice load information report triggering criteria being met, network slice load information. The steps further include determining, based on the network slice load information, that a network slice resource allocation change is needed.
    Type: Application
    Filed: December 12, 2019
    Publication date: June 17, 2021
    Inventors: Nitin Gupta, Avinash Jha, Venkatesh Aravamudhan
  • Patent number: 11031641
    Abstract: The present invention relates to an improved process and method of recovering metals of value from used Lithium Ion batteries. More particularly, the invention provides a method for recovering cobalt and lithium along with other metals of value wherein the method includes physical processes for separation, limiting the use of chemical for removing minor impurities. Majority of elements were separated by physical processes instead of chemical processes which gives the benefit of cost saving in chemical treatment of liquid and solid effluents. The invention provides for a cost effective, economic and environmental friendly process for recovering metals of value.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: June 8, 2021
    Inventors: Nitin Gupta, G. Prabaharan, Smruti Prakash Barik, Bhuvnesh Kumar
  • Patent number: 11016519
    Abstract: A voltage regulator includes an error amplifier producing an error voltage from a reference voltage and a feedback voltage. A voltage-to-current converter converts the error voltage to an output current, and a feedback resistance generates the feedback voltage from the output current. The error amplifier includes a differential pair of transistors receiving the feedback voltage and the reference voltage, a first pair of transistors operating in saturation and coupled to the differential pair of transistors at an output node and a bias node, a second pair of transistors operating in a linear region and coupled to the first pair of transistors at a pair of intermediate nodes. A compensation capacitor is coupled to one of the pair of intermediate nodes so as to compensate the error amplifier for a parasitic capacitance. An output at the output node is a function of a difference between the reference voltage and feedback voltage.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 25, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankit Gupta, Nitin Gupta, Prashutosh Gupta
  • Patent number: 10945120
    Abstract: A method for dynamically provisioning and using PLMN location mappings includes, in an SCEF or NEF, receiving, from a PLMN network node, a message containing a PLMN location identifier and a non-PLMN location identifier, extracting the PLMN location identifier and the non-PLMN location identifier from the message and storing, in a PLMN location mapping database in the SCEF or NEF, a mapping between the PLMN location identifier and the non-PLMN location identifier. The method further includes receiving, via a monitoring interface of the SCEF or NEF, a monitoring request message requesting IoT device information and including a non-PLMN location identifier.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 9, 2021
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Nitin Gupta, Raghuvamshi vasudev Singh Thakur, Venkatesh Aravamudhan
  • Publication number: 20210058766
    Abstract: A method for group device triggering for IoT devices includes receiving, from a requesting node, a device trigger request message. The method further includes determining that the device trigger request message requests group IoT device triggering. The method further includes, in response to determining that the device trigger request message requests group IoT device triggering, resolving an external group identifier in the device trigger request message to individual international mobile station identifiers (IMSIs) corresponding to target IoT devices of the device trigger request message. The method further includes signaling a downstream node to trigger the target IoT devices.
    Type: Application
    Filed: August 20, 2019
    Publication date: February 25, 2021
    Inventors: Venkatesh Aravamudhan, Anup Shivarajapura, Nitin Gupta
  • Patent number: 10929899
    Abstract: Systems and methods are provided for dynamic pricing of application programming interface (API) services such as machine learning API services. For example, a computing platform of an API service provider is configured to receive a request for a machine learning API service from a client computing device, obtain a dataset from the client computing device, utilize a classification engine to classify one or more attributes of the dataset and to classify an expected level of performance of the machine learning API service applied to the dataset based on the one or more classified attributes of the dataset, dynamically determine a pricing for the machine learning API service based on the classified expected level of performance of the dataset, and present the determined pricing for the machine learning API service on the client computing device.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Vijay Ekambaram, Nitin Gupta, Pankaj S. Dayama
  • Patent number: 10915475
    Abstract: Aspects of the disclosure provide for management of a flash translation layer (FTL) for a non-volatile memory (NVM) in a Solid State Drive (SSD). The methods and apparatus provide a logical to physical (L2P) table where a first portion of the table is used for mapping frequently accessed hot data to a first subdrive in the NVM. Additionally, a second portion of the L2P table is provided for mapping cold data less frequently accessed than the hot data to a second subdrive, where logical blocks for storing the cold data in the second subdrive are larger than logical blocks storing the hot data in the first subdrive. Separation of the L2P table into hot and cold subdrives reduces the L2P table size that is needed in RAM for logical to physical memory mapping, while at the same time provides lower write amplification and latencies, especially for large capacity SSDs.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: February 9, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rishabh Dubey, Saugata Das Purkayastha, Chaitanya Kavirayani, Sampath Raja Murthy, Nitin Gupta, Revanasiddaiah Prabhuswamy Mathada