Patents by Inventor Nitin Jain

Nitin Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240192861
    Abstract: Methods for storing control information for memory operations within spare physical blocks. During formatting of a data storage device, spare memory blocks may be identified within memory dies and placed into a spare block pool. Upon initiation of a block exchange event for a control block, a controller determines whether a spare block is available in the spare block pool. When a spare block is available, data from the control block is copied to the spare block to generate a debug block. The control block may be a MasterIndexPage block. When a spare block is not available, the controller may erase information stored in an oldest debug memory block and copy data from the control block to the oldest debug memory block.
    Type: Application
    Filed: August 10, 2023
    Publication date: June 13, 2024
    Inventors: Maharudra Nagnath Swami, G K Divya, Naveen Menezes, Nitin Jain
  • Publication number: 20240171940
    Abstract: A system for monitoring network performance includes a non-transitory computer readable medium. The non-transitory computer readable medium is configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to receive an inquiry from a user having access to a mobile device. The processor is configured to determine whether the system is able to access an application on the mobile device. The processor is configured to transmit a request to determine a location of the mobile device to the application in response to determining the system is able to access the application. The processor is configured to receive results of the location determination. The processor is configured to provide a recommendation for addressing the inquiry from the user based on the received results of the determined location.
    Type: Application
    Filed: May 17, 2022
    Publication date: May 23, 2024
    Inventors: Nitin PAL, Shivchandra PATHAK, Siddharth JAIN, Goutam AGRAWAL
  • Publication number: 20240152423
    Abstract: A read to a wordline can cause a read disturb error on neighboring wordlines. Instead of scanning the entire memory to identify wordlines that have a read disturb problem, a localized read scan approach can be used. In this approach, the memory is organized into several zones, where each zone contains several wordlines. The number of reads in each zone is tracked, and, after a certain number of reads, the data in the zone is read. If the error rate of the data exceeds a threshold, the data is relocated to another area of the memory.
    Type: Application
    Filed: July 14, 2023
    Publication date: May 9, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Maharudra Nagnath Swami, Nitin Jain
  • Patent number: 11953574
    Abstract: A magnetic resonance (MR) imaging acceleration method is provided. The method includes applying, by an MR system, a pulse sequence having a k-space trajectory of a plurality of blades being rotated in k-space, each blade including a plurality of views, wherein the k-space trajectory has an undersampling pattern in the k-space. The method also includes receiving k-space data of a subject acquired by the pulse sequence, reconstructing MR images of the subject based on the k-space data using compressed sensing, and outputting the reconstructed images.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: April 9, 2024
    Assignee: GE PRECISION HEALTHCARE LLC
    Inventors: Nitin Jain, Rajagopalan Sundaresan, Harsh Agarwal, Ramesh Venkatesan
  • Patent number: 11949164
    Abstract: Register banks are used to allow for fast beam switching in a phased array system. Each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.
    Type: Grant
    Filed: January 27, 2023
    Date of Patent: April 2, 2024
    Assignee: Anokiwave, Inc.
    Inventors: Kristian N. Madsen, Wade C. Allen, Jonathan P. Comeau, Robert J. McMorrow, David W. Corman, Nitin Jain, Robert Ian Gresham, Gaurav Menon, Vipul Jain
  • Patent number: 11928329
    Abstract: A register management system is coupled to a register. The register management system receives an address and functional data for a write operation to be performed on the register. The functional data includes write bits and mask bits associated with the write bits. One or more mask bits having a first logic state indicate that associated one or more write bits are to be written to the register, respectively. Based on the address, the register management system selects a first half of the register or a second half of the register to perform the write operation. Further, the register management system writes the one or more write bits associated with the one or more mask bits having the first logic state to one or more storage elements of the first half of the register or the second half of the register, respectively.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: March 12, 2024
    Assignee: NXP B.V.
    Inventors: Anshul Jain, Nitin Kumar Jaiswal, Sachin Prakash
  • Patent number: 11901865
    Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Nitin Jain
  • Publication number: 20240029717
    Abstract: Provided is a system to provide natural utterance by a voice assistant and method thereof, wherein the system comprises an automatic speech recognition module for converting one or more unsegmented voice inputs into textual format in real-time. Further, a natural language understanding module extracts the information and intent of the user from the converted textual inputs, wherein the natural language understanding module comprises a communication classification unit for classifying the user inputs into one or more pre-defined classes. Further, the system comprises a processing module for analyzing and processing the inputs from the natural language understanding module and activity identification module, wherein the processing module provides real-time intuitive mingling responses based on the responses, contextual pauses and ongoing activity of the user.
    Type: Application
    Filed: August 7, 2023
    Publication date: January 25, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nitin Jain, Ashutosh Gupta, Shreya Yadav
  • Publication number: 20230421101
    Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 28, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Anand KUMAR, Nitin JAIN
  • Publication number: 20230412155
    Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.
    Type: Application
    Filed: May 25, 2023
    Publication date: December 21, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Nitin JAIN, Anand KUMAR, Kallol CHATTERJEE
  • Publication number: 20230324487
    Abstract: A magnetic resonance (MR) imaging acceleration method is provided. The method includes applying, by an MR system, a pulse sequence having a k-space trajectory of a plurality of blades being rotated in k-space, each blade including a plurality of views, wherein the k-space trajectory has an undersampling pattern in the k-space. The method also includes receiving k-space data of a subject acquired by the pulse sequence, reconstructing MR images of the subject based on the k-space data using compressed sensing, and outputting the reconstructed images.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Inventors: Nitin Jain, Rajagopalan Sundaresan, Harsh Agarwal, Ramesh Venkatesan
  • Publication number: 20230275363
    Abstract: Register banks are used to allow for fast beam switching in a phased array system. Each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.
    Type: Application
    Filed: January 27, 2023
    Publication date: August 31, 2023
    Inventors: Kristian N. Madsen, Wade C. Allen, Jonathan P. Comeau, Robert J. McMorrow, David W. Corman, Nitin Jain, Robert Ian Gresham, Gaurav Menon, Vipul Jain
  • Patent number: 11728858
    Abstract: This patent application describes systems, devices, and methods for element-level self-calculation of phased array vectors by a beam forming ASIC using interpolation and a look-up table for calculation of phase setting values such as for fast beam steering.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: August 15, 2023
    Assignee: Anokiwave, Inc.
    Inventors: Jason Leo Durbin, Nitin Jain
  • Patent number: 11695216
    Abstract: A laminar phased array has a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, and a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity. The first polarity is physically orthogonal to the second polarity. The array also has a controller configured to control the first and second sub-arrays so that they operate together in either 1) a receive mode or 2) a transit mode. Accordingly, both sub-arrays are configured to operate at the same time to receive signals in the first and second polarities when in the receive mode. In a corresponding manner, both sub-arrays are configured to operate at the same time to transmit signals in the first and second polarities when in the transmit mode.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: July 4, 2023
    Assignee: Anokiwave, Inc.
    Inventors: Timothy Carey, Nitin Jain, Jason Leo Durbin, David W. Corman, Vipul Jain
  • Patent number: 11652267
    Abstract: A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: May 16, 2023
    Assignee: Anokiwave, Inc.
    Inventors: Kristian N. Madsen, Robert J. McMorrow, David W. Corman, Nitin Jain, Robert Ian Gresham, Gaurav Menon, Vipul Jain, Jonathan P. Comeau, Shmuel Ravid
  • Patent number: 11637371
    Abstract: A phased array system has a plurality of beam-forming elements, and a plurality of beam-forming integrated circuits in communication with the beam-forming elements. Each beam-forming integrated circuit has a corresponding register bank with a plurality of addressable and programmable register sets. In addition, each beam-forming integrated circuit has at least two different types of beam-forming ports. Specifically, each beam-forming element has a serial data port for receiving serial messages, and a parallel mode data port for receiving broadcast messages. Both the serial and broadcast messages manage the data in its register bank. The beam-forming integrated circuits receive the broadcast messages in parallel with the other beam-forming integrated circuits, while the beam-forming integrated circuits receive the serial messages serially—sequentially with regard to other beam-forming integrated circuits.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: April 25, 2023
    Assignee: Anokiwave, Inc.
    Inventors: Vipul Jain, Scott Humphreys, David W. Corman, Robert Ian Gresham, Kristian N. Madsen, Robert J. McMorrow, Jonathan P. Comeau, Nitin Jain, Gaurav Menon
  • Publication number: 20230114753
    Abstract: A method of diagnosis and treatment of primary biliary cholangitis is provided. Additionally, a pharmaceutical composition and a solid dosage form for the treatment of primary biliary cholangitis, containing ursodeoxycholic and obeticholic acids, are provided. The technical contribution resides in obtaining a new all-purpose pharmaceutical composition and solid dosage form for the treatment of PBC, which includes both ursodeoxycholic and obeticholic acids, which is effective in use at all stages of PBC and has a complex mechanism of action. In particular, simultaneous blockage of the transport and synthesis of bile acids is achieved.
    Type: Application
    Filed: March 8, 2021
    Publication date: April 13, 2023
    Inventor: Nitin JAIN
  • Publication number: 20230090782
    Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 23, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Anand KUMAR, Nitin JAIN
  • Patent number: 11418971
    Abstract: A beamforming integrated circuit system is configured to optimize performance. Among other things, the system may run at a lower power than conventional integrated circuits, selectively disable branches to control certain system functions, and/or selectively position ground pads around receiving pads to enhance isolation. The system also may use a beamforming integrated circuit as a distribution circuit for a number of similar or like beamforming integrated circuits.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: August 16, 2022
    Assignee: Anokiwave, Inc.
    Inventors: Pavel Brechko, David W. Corman, Vipul Jain, Shamsun Nahar, Jason Durbin, Nitin Jain
  • Publication number: 20220200162
    Abstract: A laminar phased array has a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, and a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity. The first polarity is physically orthogonal to the second polarity. The array also has a controller configured to control the first and second sub-arrays so that they operate together in either 1) a receive mode or 2) a transit mode. Accordingly, both sub-arrays are configured to operate at the same time to receive signals in the first and second polarities when in the receive mode. In a corresponding manner, both sub-arrays are configured to operate at the same time to transmit signals in the first and second polarities when in the transmit mode.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 23, 2022
    Inventors: Timothy Carey, Nitin Jain, Jason Leo Durbin, David W. Corman, Vipul Jain