Abstract: A beamforming integrated circuit (BFIC), including a first port configured to receive a first radio frequency (RF) signal; a second port configured to receive a second RF signal; and one or more routing devices disposed between the first port and the second port. The one or more routing devices are configured to route one of the first RF signal or the second RF signal to merge with another one of the first RF signal and the second RF signal in a merging line.

Abstract: A process monitoring technique for transistor-based devices is described. The technique utilizes an oscillator-based sensor and operates in two phases: calibration and measurement. During calibration, the oscillator is supplied with a calibration current, and the resulting frequency is measured. A correction factor is calculated by dividing the measured frequency by the calibration current. In the measurement phase, the oscillator is supplied with current from the device under test, such as a memory cell or other transistor-based structure. The frequency produced is measured and divided by the correction factor to determine the current from the device. This approach yields a current value independent of parasitic resistances and capacitances in the oscillator. The technique enables accurate process variation monitoring with little modification to existing circuit structures and is applicable to various transistor-based devices, including SRAM cells, logic circuits, and analog circuits.

Abstract: The invention relates to the field of medicine, in particular to solid dosage forms for the treatment of primary biliary cholangitis (PBC). The invention provides a modified release solid dosage form comprising two active pharmaceutical ingredients, obeticholic acid and ursodeoxycholic acid, arranged to release sequentially over time. The solid dosage form is designed to achieve a controlled, separate release of each API to provide a desired therapeutic profile.

Abstract: A low-power clock buffer circuit is disclosed that reduces crowbar current and improves power efficiency across a wide range of supply voltages. The circuit comprises an input stage with current-limited PMOS and NMOS transistors, and an output inverter stage with split-gate drive. The input stage uses current sources to control the rise and fall times of signals driving the output inverter, creating a delay between the activation of the PMOS and NMOS transistors in the output stage. This delay minimizes the duration when both output transistors are simultaneously conducting, significantly reducing crowbar current. An alternative embodiment includes a current-starved latch in the output stage to mitigate floating node situations and enhance signal integrity. The circuit is suitable for clock distribution networks in large digital systems.

Abstract: In accordance with various embodiments of the present disclosure, a circuit to provide a reference current to a device having a first current controlled oscillator (CCO) is provided. In some embodiments, the circuit comprises a reference circuit and a feedback loop circuit. The feedback loop circuit comprises a differential circuit that receives an input voltage from the reference circuit and provides an output current, a second CCO that receives the output current from the differential circuit and produces an output frequency in response, a divider circuit to divide the output frequency into a feedback frequency, and a feedback switched capacitor resistor circuit providing a feedback voltage to the differential circuit based on the feedback frequency. The second CCO has substantially matching performance to the first CCO. The differential circuit adjusts its output current based on a difference between the input voltage and the feedback voltage.

Abstract: The disclosure relates to a method and a system for text presentation in an augmented reality (AR) based device. The method comprises: identifying one or more layout types for a complete text; restructuring the complete text based on one or more visual see through (VST) parameters, the one or more layout types, and a text occupancy per degree value; identifying a text position for the restructured text based on at least one of: one or more user parameters, one or more user activities, and the one or more VST parameters; and presenting the restructured text based on the identified text position.

Abstract: Provided is a system to provide natural utterance by a voice assistant and method thereof, wherein the system comprises an automatic speech recognition module for converting one or more unsegmented voice inputs into textual format in real-time. Further, a natural language understanding module extracts the information and intent of the user from the converted textual inputs, wherein the natural language understanding module comprises a communication classification unit for classifying the user inputs into one or more pre-defined classes. Further, the system comprises a processing module for analyzing and processing the inputs from the natural language understanding module and activity identification module, wherein the processing module provides real-time intuitive mingling responses based on the responses, contextual pauses and ongoing activity of the user.

Abstract: A method for seamless video capture during flex-state transition in a foldable device includes identifying, by one or more sensors of the foldable device, an initiation of a flex movement of the foldable device based on a plurality of frames of a video being captured by a source camera from among one or more cameras of the foldable device; extracting, based on the identifying of the initiation of the flex movement, a semantic scene from the plurality of frames to determine one or more regions of interest (ROIs) in the semantic scene; determining an optical flow for each of the one or more ROIs; determining a flex trajectory of the foldable device; determining a target camera from among the one or more cameras; determining a transition period to switch to the target camera; and switching capturing of the plurality of frames from the source camera to the target camera.

Abstract: A storage device may recover from an uncorrectable read failure in a control block. The storage device includes a memory device divided into blocks. The blocks on the memory device may include control blocks for storing control information for accessing host data. A controller on the storage device may identify when an uncorrectable read failure occurs in a first control block. The controller may quarantine the first control block and notify a host device of the uncorrectable read failure. Based on a response from the host device, the controller may recover the storage device to operate in a normal mode such that a recovered storage device excludes the first control block from use.

Abstract: Systems and methods are disclosed for providing host-independent format operations in data storage devices. In certain embodiments, a data storage device includes a non-volatile memory; a pinhole button configured to be pressed; and a controller configured to: detect that the pinhole button is pressed; detect that the data storage device is coupled to a direct-current (DC) power supply; and initiate formatting of the data storage device or a factory reset of the data storage device.

Abstract: A computer-implemented method for generating a magnetic resonance (MR) image of an object includes applying, via a processing system comprising one or more processors, a Hadamard encoded radiofrequency (RF) excitation pulse sequence to adjacent slices within a magnetic resonance imaging (MRI) scanner to generate Hadamard encoded adjacent slices; multiplexing, via the processing system, the Hadamard encoded adjacent slices with secondary RF excitation pulses to generate a composite RF pulse; and generating, via the processing system, the MR image of the object using the composite RF pulse.

Abstract: A storage device may recover from an uncorrectable read failure in a control block. The storage device includes a memory device divided into blocks. The blocks on the memory device may include control blocks for storing control information for accessing host data. A controller on the storage device may identify when an uncorrectable read failure occurs in a first control block. The controller may quarantine the first control block and notify a host device of the uncorrectable read failure. Based on a response from the host device, the controller may recover the storage device to operate in a normal mode such that a recovered storage device excludes the first control block from use.

Abstract: A storage device postpones entry into a read-only mode due to faulty blocks that cannot be written to on a memory device. The memory device is divided into blocks. Blocks used for storing host data are placed in a main area pool, blocks used for storing host data and for peak write operations are placed in a burst pool, and blocks used for storing control information are placed in the control pool. A controller executes a read-only mode extension protocol to determine when a number of faulty blocks in the main area pool, control pool, or burst pool is approaching a threshold for placing the storage device in a read-only mode. If the storage device is approaching the read-only mode, the controller reduces and/or repurposes a number of the blocks used for storing host data in the burst pool to prevent the storage device from entering the read-only mode phase.

Abstract: Systems and methods are disclosed for providing host-independent data operations. In certain embodiments, a data storage device includes a non-volatile memory; a pinhole button configured to be pressed; and a controller configured to: detect that the pinhole button is pressed; detect that the data storage device is coupled to a direct-current (DC) power supply; and initiate a disk operation for the data storage device. In some embodiments, the controller can be configured to initiate a data operation, such as an authentication or data accessibility operation, a data security operation, etc., for example, in addition to or instead of a disk operation.

Abstract: A storage device postpones entry into a read-only mode due to faulty blocks that cannot be written to on a memory device. The memory device is divided into blocks. Blocks used for storing host data are placed in a main area pool, blocks used for storing host data and for peak write operations are placed in a burst pool, and blocks used for storing control information are placed in the control pool. A controller executes a read-only mode extension protocol to determine when a number of faulty blocks in the main area pool, control pool, or burst pool is approaching a threshold for placing the storage device in a read-only mode. If the storage device is approaching the read-only mode, the controller reduces and/or repurposes a number of the blocks used for storing host data in the burst pool to prevent the storage device from entering the read-only mode phase.

Abstract: A memory block recovery process is used to review and recover memory blocks of a memory device that have potentially been misidentified as bad blocks. The memory block recovery process is initiated when a threshold number of entries in a failed memory block list is exceeded. During the memory block recovery process, the failed memory block list is analyzed to determine whether there is any correlation between memory blocks that failed programming operations and memory blocks that were programmed prior to the memory block failing its programming operation. If there is a correlation, an independent program operation is performed on each memory block that failed its programming operation. If the independent programming operation on the memory block is successful, the memory block is reclaimed and the prior programmed memory block is identified as a bad block.

Abstract: A method includes obtaining k-space data acquired by an MRI scanner from a single channel body coil utilizing a multi-shot EP-DWI pulse sequence and sampling the k-space data for a plurality of shots so that for each shot both a central k-space is fully sampled to form a central calibration region and an outer k-space is partially sampled by a factor equal to a number of shots. The method includes reconstructing an initial fully sampled k-space estimate for each shot utilizing both partial Fourier constant sampling and projection on convex sets reconstruction, wherein the plurality of shots is treated as a plurality of channels for filling in missing k-space for a respective shot. The method includes utilizing a low-rank regularization algorithm in an iterative manner to generate a reconstructed image for each shot, wherein the initial fully sampled k-space estimate for each shot is utilized as an initial guess.

Abstract: Register banks are used to allow for fast beam switching in a phased array system. Each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.

Abstract: A data storage device includes storage media and control circuitry and is configured to enable the creation of partitions with different performance levels. The storage media includes a first set and a second set of memory blocks having different performance levels. The control circuitry is configured to: in response to a request from a host system, provide performance data from the first set of memory blocks and the second set of memory blocks to the host system. The control circuitry is further configured to: receive partition settings from the host system, the partition settings creating a first partition including at least part of the first set of memory blocks and a second partition including at least part of the second set of memory blocks, wherein the first partition has a better performance level than the second partition; and save the partition settings to the storage media.