Abstract: Register banks are used to allow for fast beam switching in a phased array system. Each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.

Abstract: A data storage device includes storage media and control circuitry and is configured to enable the creation of partitions with different performance levels. The storage media includes a first set and a second set of memory blocks having different performance levels. The control circuitry is configured to: in response to a request from a host system, provide performance data from the first set of memory blocks and the second set of memory blocks to the host system. The control circuitry is further configured to: receive partition settings from the host system, the partition settings creating a first partition including at least part of the first set of memory blocks and a second partition including at least part of the second set of memory blocks, wherein the first partition has a better performance level than the second partition; and save the partition settings to the storage media.

Abstract: A method for seamless video capture during flex-state transition in a foldable device includes identifying, by one or more sensors of the foldable device, an initiation of a flex movement of the foldable device based on a plurality of frames of a video being captured by a source camera from among one or more cameras of the foldable device; extracting, based on the identifying of the initiation of the flex movement, a semantic scene from the plurality of frames to determine one or more regions of interest (ROIs) in the semantic scene; determining an optical flow for each of the one or more ROIs; determining a flex trajectory of the foldable device; determining a target camera from among the one or more cameras; determining a transition period to switch to the target camera; and switching capturing of the plurality of frames from the source camera to the target camera.

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

Abstract: Methods for storing control information for memory operations within spare physical blocks. During formatting of a data storage device, spare memory blocks may be identified within memory dies and placed into a spare block pool. Upon initiation of a block exchange event for a control block, a controller determines whether a spare block is available in the spare block pool. When a spare block is available, data from the control block is copied to the spare block to generate a debug block. The control block may be a MasterIndexPage block. When a spare block is not available, the controller may erase information stored in an oldest debug memory block and copy data from the control block to the oldest debug memory block.

Abstract: A read to a wordline can cause a read disturb error on neighboring wordlines. Instead of scanning the entire memory to identify wordlines that have a read disturb problem, a localized read scan approach can be used. In this approach, the memory is organized into several zones, where each zone contains several wordlines. The number of reads in each zone is tracked, and, after a certain number of reads, the data in the zone is read. If the error rate of the data exceeds a threshold, the data is relocated to another area of the memory.

Abstract: Systems and methods are disclosed for providing host-independent format operations in data storage devices. In certain embodiments, a data storage device includes a non-volatile memory; a pinhole button configured to be pressed; and a controller configured to: detect that the pinhole button is pressed; detect that the data storage device is coupled to a direct-current (DC) power supply; and initiate formatting of the data storage device or a factory reset of the data storage device.

Abstract: Systems and methods are disclosed for providing host-independent disk optimization and data operations. In certain embodiments, a data storage device includes a non-volatile memory; a pinhole button configured to be pressed; and a controller configured to: detect that the pinhole button is pressed; detect that the data storage device is coupled to a direct-current (DC) power supply; and initiate a disk optimization operation for the data storage device. In some embodiments, the controller can be configured to initiate a data operation, such as an authentication or data accessibility operation, a data security operation, etc., for example, in addition to or instead of a disk optimization operation.

Abstract: A data storage device includes storage media and control circuitry and is configured to enable the creation of partitions with different performance levels. The storage media includes a first set and a second set of memory blocks having different performance levels. The control circuitry is configured to: in response to a request from a host system, provide performance data from the first set of memory blocks and the second set of memory blocks to the host system. The control circuitry is further configured to: receive partition settings from the host system, the partition settings creating a first partition including at least part of the first set of memory blocks and a second partition including at least part of the second set of memory blocks, wherein the first partition has a better performance level than the second partition; and save the partition settings to the storage media.

Abstract: Some areas (e.g., boundary wordlines) in a block of memory can be more error prone than others. Typically, errors in these areas are not detected until after the entire block is programmed. Handling such errors then can result in performance penalties and large data relocations. With the embodiments presented herein, a two-stage programming operation is provided. In the first stage, only the error-prone areas of the block are programmed, and a check is made to determine if an error occurred in that programming. In the second stage, the remaining portions of the block are programmed, but that only occurs after it is determined that the error-prone areas have been programmed successfully. Detecting and dealing with errors in the error-prone areas before the entire block is programmed avoid the performance penalties and large data relocations noted above.

Abstract: A method includes obtaining k-space data acquired by an MRI scanner from a single channel body coil utilizing a multi-shot EP-DWI pulse sequence and sampling the k-space data for a plurality of shots so that for each shot both a central k-space is fully sampled to form a central calibration region and an outer k-space is partially sampled by a factor equal to a number of shots. The method includes reconstructing an initial fully sampled k-space estimate for each shot utilizing both partial Fourier constant sampling and projection on convex sets reconstruction, wherein the plurality of shots is treated as a plurality of channels for filling in missing k-space for a respective shot. The method includes utilizing a low-rank regularization algorithm in an iterative manner to generate a reconstructed image for each shot, wherein the initial fully sampled k-space estimate for each shot is utilized as an initial guess.

Abstract: Some areas (e.g., boundary wordlines) in a block of memory can be more error prone than others. Typically, errors in these areas are not detected until after the entire block is programmed. Handling such errors then can result in performance penalties and large data relocations. With the embodiments presented herein, a two-stage programming operation is provided. In the first stage, only the error-prone areas of the block are programmed, and a check is made to determine if an error occurred in that programming. In the second stage, the remaining portions of the block are programmed, but that only occurs after it is determined that the error-prone areas have been programmed successfully. Detecting and dealing with errors in the error-prone areas before the entire block is programmed avoid the performance penalties and large data relocations noted above.

Abstract: The present disclosure provides antibodies and antigen-binding domain compositions capable of binding to thymic stromal lymphopoietin receptor (TSLPR). Also provided are methods of using such antibodies for the treatment of TSLPR-associated cancers (e.g., B-Cell Acute Lymphoblastic Leukemia (B-ALL)). In embodiments, the antibodies are heterodimeric antibodies that bind TSLPR and CD3 epsilon (i.e., anti-TSLPR x anti-CD3e) antibodies.

Abstract: Register banks are used to allow for fast beam switching in a phased array system. Each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: A memory block recovery process is used to review and recover memory blocks of a memory device that have potentially been misidentified as bad blocks. The memory block recovery process is initiated when a threshold number of entries in a failed memory block list is exceeded. During the memory block recovery process, the failed memory block list is analyzed to determine whether there is any correlation between memory blocks that failed programming operations and memory blocks that were programmed prior to the memory block failing its programming operation. If there is a correlation, an independent program operation is performed on each memory block that failed its programming operation. If the independent programming operation on the memory block is successful, the memory block is reclaimed and the prior programmed memory block is identified as a bad block.

Abstract: The present disclosure generally relates to improved wait time notifications from SSDs to host systems. Rather than assuming on when to restart an SSD after an asynchronous event notification (AEN) is sent, issuing a cool-off wait time. When an SSD is overheating, an AEN is sent from the SSD. An AEN may either be a warning event or a critical event. Once the AEN is received, a host may issue a banner with a cool-off wait time. The cool-off wait time is a predetermined time that will begin if the SSD is not detected by host systems. A non-detectable SSD means that the SSD is in a thermal shut down mode, which is initiated by a PMIC. In the thermal shut down mode, the cool-off wait timer will begin at host side. After the time has elapsed the SSD can then be restarted either manually by user or automatically by host.

Abstract: An AON module on a storage device periodically obtains the temperatures of the storage device and memory device. A controller uses the temperatures obtained by the AON module to determine a calculated temperature. The controller determines when the calculated temperature is above a thermal threshold and causes the storage device to enter the thermal sleep state where normal operations on the storage device are suspended. In the thermal sleep state, power to the AON module is maintained and the power to other components is modified. The AON module starts a cool-off timer and after a cool-off time expires, the AON module causes power to at least one component on the storage device to be turned on to determine whether the temperature of the storage device is below a first thermal throttling threshold and to cause the storage device to resume normal operations.

Abstract: Methods for storing control information for memory operations within spare physical blocks. During formatting of a data storage device, spare memory blocks may be identified within memory dies and placed into a spare block pool. Upon initiation of a block exchange event for a control block, a controller determines whether a spare block is available in the spare block pool. When a spare block is available, data from the control block is copied to the spare block to generate a debug block. The control block may be a MasterIndexPage block. When a spare block is not available, the controller may erase information stored in an oldest debug memory block and copy data from the control block to the oldest debug memory block.

Abstract: A read to a wordline can cause a read disturb error on neighboring wordlines. Instead of scanning the entire memory to identify wordlines that have a read disturb problem, a localized read scan approach can be used. In this approach, the memory is organized into several zones, where each zone contains several wordlines. The number of reads in each zone is tracked, and, after a certain number of reads, the data in the zone is read. If the error rate of the data exceeds a threshold, the data is relocated to another area of the memory.