Patents by Inventor Nitin Jain

Nitin Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250081157
    Abstract: Techniques for identifying locations of network devices in a fabric network. The method includes a network controller and/or control plane of a network fabric coupled to an access switch at a software-defined access (SDA) site. At least one mapping is registered at the SDA site and sent with the location data from the access switch to the network controller. The network controller and/or control plane is configured to at least one of to learn, update, and publish location data of a destination address from at least one mapping received from the access switch by the location data being associated with a mapping at the SDA site and destination address. The network controller identifies the location of the destination address from a received request based on associating the destination address with the location learned from the location data of at least one mapping that has been registered at the SDA site.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 6, 2025
    Inventors: Prakash C. Jain, Aaditya Nitin Vadnere, Parthiv Shah
  • Patent number: 12228493
    Abstract: A microfluidic impedance cytometry apparatus, for position determination and impedance measurement of particle/s in a fluid carrying particles, comprising: a microfluidic impedance flow channel for allowing flow of said fluid; an upstream section; a downstream section; a sensing region to receive said channeled fluid, to sense one or more parameters of said fluid, said sensing region comprising one or more sets of pairs of electrodes, each pair forming a current path from an operative top to an operative bottom, each of said pairs being formed by an operative top electrode and an operative bottom electrode, electric potential being applied on said operative top electrode/s, each electrode for a particular pair being parallel-aligned and being symmetric, with respect to each other, same positive electric potential being applied on each of said top electrodes and each of said bottom electrodes is virtually grounded, for a pair; and a configuration of amplifiers.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: February 18, 2025
    Assignee: MICROX LABS INC.
    Inventors: Usama Ahmed Abbasi, Nitin C M, Sushant Kumar, Prakhar Jain
  • Publication number: 20250056132
    Abstract: A method for seamless video capture during flex-state transition in a foldable device includes identifying, by one or more sensors of the foldable device, an initiation of a flex movement of the foldable device based on a plurality of frames of a video being captured by a source camera from among one or more cameras of the foldable device; extracting, based on the identifying of the initiation of the flex movement, a semantic scene from the plurality of frames to determine one or more regions of interest (ROIs) in the semantic scene; determining an optical flow for each of the one or more ROIs; determining a flex trajectory of the foldable device; determining a target camera from among the one or more cameras; determining a transition period to switch to the target camera; and switching capturing of the plurality of frames from the source camera to the target camera.
    Type: Application
    Filed: August 9, 2024
    Publication date: February 13, 2025
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sai Hemanth KASARANENI, Nitin JAIN, Gunit ANAND, Chhavi YADAV, Baljeet KUMAR
  • Patent number: 12224710
    Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: February 11, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Nitin Jain
  • Patent number: 12210418
    Abstract: A method, non-transitory computer readable medium, and a system for pre-backup anomalous object detection and exclusion rule creation. Enterprise information technology environments often include any number of assets maintaining vast quantities of data and state. Any asset, in turn, may be riddled with various anomalous objects that tend to cause backup failure. Embodiments described herein address backup failure due to the presence of anomalous objects by, during a pre-backup stage, examining any number of assets to identify any anomalous objects there-within. Once identified, the anomalous object(s) (or metadata descriptive thereof) may be recorded within a backup skip list and, subsequently, excluded from the current and/or any future backup(s). Exclusion of the anomalous object(s), from said backup(s), may be enforced through the automatic creation of one or many exclusion rule(s) that impact, and thus adjust, the backup policy/policies associated with the asset(s).
    Type: Grant
    Filed: April 11, 2023
    Date of Patent: January 28, 2025
    Assignee: DELL PRODUCTS L.P.
    Inventors: Aaditya Rakesh, Upanshu Singhal, Nancy Jain, Nitin Kumar
  • Publication number: 20250030705
    Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to prevent data loss, including determining a multi-layered security protocol from a plurality of security protocols stored in a database, after a determination that the multi-layered security protocol includes at least one security protocol corresponding to each unique type, causing the multi-layered security protocol to be enabled, after a breach of the multi-layered security protocol, performing an enforcement, the enforcement to include using a third-party integration and notifying a developer.
    Type: Application
    Filed: October 19, 2023
    Publication date: January 23, 2025
    Inventors: SHARADENDU PRAKASH SINHA, SIDDHARTH SUKUMAR BURLE, MANISH JAIN, NITIN KOTHARI, SACHIN MAHAJAN
  • Patent number: 12197284
    Abstract: A read to a wordline can cause a read disturb error on neighboring wordlines. Instead of scanning the entire memory to identify wordlines that have a read disturb problem, a localized read scan approach can be used. In this approach, the memory is organized into several zones, where each zone contains several wordlines. The number of reads in each zone is tracked, and, after a certain number of reads, the data in the zone is read. If the error rate of the data exceeds a threshold, the data is relocated to another area of the memory.
    Type: Grant
    Filed: July 14, 2023
    Date of Patent: January 14, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Maharudra Nagnath Swami, Nitin Jain
  • Patent number: 12197744
    Abstract: Methods for storing control information for memory operations within spare physical blocks. During formatting of a data storage device, spare memory blocks may be identified within memory dies and placed into a spare block pool. Upon initiation of a block exchange event for a control block, a controller determines whether a spare block is available in the spare block pool. When a spare block is available, data from the control block is copied to the spare block to generate a debug block. The control block may be a MasterIndexPage block. When a spare block is not available, the controller may erase information stored in an oldest debug memory block and copy data from the control block to the oldest debug memory block.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: January 14, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Maharudra Nagnath Swami, G K Divya, Naveen Menezes, Nitin Jain
  • Publication number: 20240427501
    Abstract: Systems and methods are disclosed for providing host-independent disk optimization and data operations. In certain embodiments, a data storage device includes a non-volatile memory; a pinhole button configured to be pressed; and a controller configured to: detect that the pinhole button is pressed; detect that the data storage device is coupled to a direct-current (DC) power supply; and initiate a disk optimization operation for the data storage device. In some embodiments, the controller can be configured to initiate a data operation, such as an authentication or data accessibility operation, a data security operation, etc., for example, in addition to or instead of a disk optimization operation.
    Type: Application
    Filed: August 9, 2023
    Publication date: December 26, 2024
    Inventor: Nitin Jain
  • Publication number: 20240427509
    Abstract: Systems and methods are disclosed for providing host-independent format operations in data storage devices. In certain embodiments, a data storage device includes a non-volatile memory; a pinhole button configured to be pressed; and a controller configured to: detect that the pinhole button is pressed; detect that the data storage device is coupled to a direct-current (DC) power supply; and initiate formatting of the data storage device or a factory reset of the data storage device.
    Type: Application
    Filed: August 9, 2023
    Publication date: December 26, 2024
    Inventor: Nitin Jain
  • Publication number: 20240411469
    Abstract: A data storage device includes storage media and control circuitry and is configured to enable the creation of partitions with different performance levels. The storage media includes a first set and a second set of memory blocks having different performance levels. The control circuitry is configured to: in response to a request from a host system, provide performance data from the first set of memory blocks and the second set of memory blocks to the host system. The control circuitry is further configured to: receive partition settings from the host system, the partition settings creating a first partition including at least part of the first set of memory blocks and a second partition including at least part of the second set of memory blocks, wherein the first partition has a better performance level than the second partition; and save the partition settings to the storage media.
    Type: Application
    Filed: August 11, 2023
    Publication date: December 12, 2024
    Inventors: Nitin JAIN, Ronak JAIN, Matthew KLAPMAN, Ramanathan MUTHIAH, Taninder Singh SIJHER
  • Patent number: 12153804
    Abstract: Some areas (e.g., boundary wordlines) in a block of memory can be more error prone than others. Typically, errors in these areas are not detected until after the entire block is programmed. Handling such errors then can result in performance penalties and large data relocations. With the embodiments presented herein, a two-stage programming operation is provided. In the first stage, only the error-prone areas of the block are programmed, and a check is made to determine if an error occurred in that programming. In the second stage, the remaining portions of the block are programmed, but that only occurs after it is determined that the error-prone areas have been programmed successfully. Detecting and dealing with errors in the error-prone areas before the entire block is programmed avoid the performance penalties and large data relocations noted above.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: November 26, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Nitin Jain, Maharudra Nagnath Swami
  • Publication number: 20240385274
    Abstract: A method includes obtaining k-space data acquired by an MRI scanner from a single channel body coil utilizing a multi-shot EP-DWI pulse sequence and sampling the k-space data for a plurality of shots so that for each shot both a central k-space is fully sampled to form a central calibration region and an outer k-space is partially sampled by a factor equal to a number of shots. The method includes reconstructing an initial fully sampled k-space estimate for each shot utilizing both partial Fourier constant sampling and projection on convex sets reconstruction, wherein the plurality of shots is treated as a plurality of channels for filling in missing k-space for a respective shot. The method includes utilizing a low-rank regularization algorithm in an iterative manner to generate a reconstructed image for each shot, wherein the initial fully sampled k-space estimate for each shot is utilized as an initial guess.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 21, 2024
    Inventors: Nitin Jain, Ashok Kumar P Reddy, Rajdeep Das, Sajith Rajamani, Rajagopalan Sundaresan, Harsh Kumar Agarwal, Ramesh Venkatesan
  • Publication number: 20240377961
    Abstract: Some areas (e.g., boundary wordlines) in a block of memory can be more error prone than others. Typically, errors in these areas are not detected until after the entire block is programmed. Handling such errors then can result in performance penalties and large data relocations. With the embodiments presented herein, a two-stage programming operation is provided. In the first stage, only the error-prone areas of the block are programmed, and a check is made to determine if an error occurred in that programming. In the second stage, the remaining portions of the block are programmed, but that only occurs after it is determined that the error-prone areas have been programmed successfully. Detecting and dealing with errors in the error-prone areas before the entire block is programmed avoid the performance penalties and large data relocations noted above.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 14, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Nitin Jain, Maharudra Nagnath Swami
  • Publication number: 20240360233
    Abstract: The present disclosure provides antibodies and antigen-binding domain compositions capable of binding to thymic stromal lymphopoietin receptor (TSLPR). Also provided are methods of using such antibodies for the treatment of TSLPR-associated cancers (e.g., B-Cell Acute Lymphoblastic Leukemia (B-ALL)). In embodiments, the antibodies are heterodimeric antibodies that bind TSLPR and CD3 epsilon (i.e., anti-TSLPR x anti-CD3e) antibodies.
    Type: Application
    Filed: August 27, 2022
    Publication date: October 31, 2024
    Inventors: Dongxing ZHA, Marina KONOPLEVA, Nitin JAIN, Melinda G. SMITH, Ze TIAN, Jason K. ALLEN, Chunhua SHI, Amin AL-SHAMI, Alex NISTHAL, John R. DESJARLAIS, Seung CHU, Erik PONG
  • Publication number: 20240347930
    Abstract: Register banks are used to allow for fast beam switching in a phased array system. Each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.
    Type: Application
    Filed: March 5, 2024
    Publication date: October 17, 2024
    Inventors: Kristian N. Madsen, Wade C. Allen, Jonathan P. Comeau, Robert J. McMorrow, David W. Corman, Nitin Jain, Robert Ian Gresham, Gaurav Menon, Vipul Jain
  • Publication number: 20240330117
    Abstract: A memory block recovery process is used to review and recover memory blocks of a memory device that have potentially been misidentified as bad blocks. The memory block recovery process is initiated when a threshold number of entries in a failed memory block list is exceeded. During the memory block recovery process, the failed memory block list is analyzed to determine whether there is any correlation between memory blocks that failed programming operations and memory blocks that were programmed prior to the memory block failing its programming operation. If there is a correlation, an independent program operation is performed on each memory block that failed its programming operation. If the independent programming operation on the memory block is successful, the memory block is reclaimed and the prior programmed memory block is identified as a bad block.
    Type: Application
    Filed: July 24, 2023
    Publication date: October 3, 2024
    Inventors: Nitin Jain, Maharudra Nagnath Swami, Naveen Menezes
  • Publication number: 20240232070
    Abstract: An AON module on a storage device periodically obtains the temperatures of the storage device and memory device. A controller uses the temperatures obtained by the AON module to determine a calculated temperature. The controller determines when the calculated temperature is above a thermal threshold and causes the storage device to enter the thermal sleep state where normal operations on the storage device are suspended. In the thermal sleep state, power to the AON module is maintained and the power to other components is modified. The AON module starts a cool-off timer and after a cool-off time expires, the AON module causes power to at least one component on the storage device to be turned on to determine whether the temperature of the storage device is below a first thermal throttling threshold and to cause the storage device to resume normal operations.
    Type: Application
    Filed: September 25, 2023
    Publication date: July 11, 2024
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: NITIN JAIN, SRIKANTH PEDDAYYAVANDLA
  • Publication number: 20240231962
    Abstract: The present disclosure generally relates to improved wait time notifications from SSDs to host systems. Rather than assuming on when to restart an SSD after an asynchronous event notification (AEN) is sent, issuing a cool-off wait time. When an SSD is overheating, an AEN is sent from the SSD. An AEN may either be a warning event or a critical event. Once the AEN is received, a host may issue a banner with a cool-off wait time. The cool-off wait time is a predetermined time that will begin if the SSD is not detected by host systems. A non-detectable SSD means that the SSD is in a thermal shut down mode, which is initiated by a PMIC. In the thermal shut down mode, the cool-off wait timer will begin at host side. After the time has elapsed the SSD can then be restarted either manually by user or automatically by host.
    Type: Application
    Filed: July 26, 2023
    Publication date: July 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Nitin JAIN, Srikanth PEDDAYYAVANDLA
  • Publication number: 20240192861
    Abstract: Methods for storing control information for memory operations within spare physical blocks. During formatting of a data storage device, spare memory blocks may be identified within memory dies and placed into a spare block pool. Upon initiation of a block exchange event for a control block, a controller determines whether a spare block is available in the spare block pool. When a spare block is available, data from the control block is copied to the spare block to generate a debug block. The control block may be a MasterIndexPage block. When a spare block is not available, the controller may erase information stored in an oldest debug memory block and copy data from the control block to the oldest debug memory block.
    Type: Application
    Filed: August 10, 2023
    Publication date: June 13, 2024
    Inventors: Maharudra Nagnath Swami, G K Divya, Naveen Menezes, Nitin Jain