Patents by Inventor Nitin K. Ingle

Nitin K. Ingle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11830729
    Abstract: Exemplary methods of semiconductor processing may include providing a boron-and-carbon-and-nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include generating a capacitively-coupled plasma of the boron-and-carbon-and-nitrogen-containing precursor. The methods may include forming a boron-and-carbon-and-nitrogen-containing layer on the substrate. The boron-and-carbon-and-nitrogen-containing layer may be characterized by a dielectric constant below or about 3.5.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: November 28, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 11818877
    Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: November 14, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Sung-Kwan Kang, Fredrick Fishburn, Gill Yong Lee, Nitin K. Ingle
  • Patent number: 11791155
    Abstract: Examples of the present technology include semiconductor processing methods to form diffusion barriers for germanium in a semiconductor structure. The methods may include forming a semiconductor layer stack from pairs of Si-and-SiGe layers. The Si-and-SiGe layer pairs may be formed by forming a silicon layer, and then forming the germanium barrier layer of the silicon layer. In some embodiments, the germanium-barrier layer may be less than or about 20 ?. A silicon-germanium layer may be formed on the germanium-barrier layer to complete the formation of the Si-and-SiGe layer pair. In some embodiments, the silicon layer may be an amorphous silicon layer, and the SiGe layer may be characterized by greater than or about 5 atom % germanium. Examples of the present technology also include semiconductor structures that include a silicon-germanium layer, a germanium-barrier layer, and a silicon layer.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: October 17, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Huiyuan Wang, Susmit Singha Roy, Takehito Koshizawa, Bo Qi, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 11735467
    Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: August 22, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Ashish Pal, Gaurav Thareja, Sankuei Lin, Ching-Mei Hsu, Nitin K. Ingle, Ajay Bhatnagar, Anchuan Wang
  • Patent number: 11732352
    Abstract: Hydrogen free (low-H) silicon dioxide layers are disclosed. Some embodiments provide methods for forming low-H layers using hydrogen-free silicon precursors and hydrogen-free oxygen sources. Some embodiments provide methods for tuning the stress profile of low-H silicon dioxide films. Further, some embodiments of the disclosure provide oxide-nitride stacks which exhibit reduced stack bow after anneal.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: August 22, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 11696433
    Abstract: Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: July 4, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Nitin K. Ingle, Fredrick Fishburn
  • Publication number: 20230157004
    Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.
    Type: Application
    Filed: January 13, 2023
    Publication date: May 18, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Nitin K. Ingle, Sung-Kwan Kang
  • Publication number: 20230096309
    Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Chang Seok KANG, Tomohiko KITAJIMA, Sung-Kwan KANG, Fredrick FISHBURN, Gill Yong LEE, Nitin K. INGLE
  • Publication number: 20230068312
    Abstract: Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.
    Type: Application
    Filed: August 29, 2022
    Publication date: March 2, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Suketu Arun Parikh, Ashish Pal, El Mehdi Bazizi, Andrew Yeoh, Nitin K. Ingle, Arvind Sundarrajan, Guan Huei See, Martinus Maria Berkens, Sameer A. Deshpande, Balasubramanian Pranatharthiharan, Yen-Chu Yang
  • Publication number: 20230061392
    Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.
    Type: Application
    Filed: August 29, 2022
    Publication date: March 2, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Suketu Arun Parikh, Ashish Pal, El Mehdi Bazizi, Andrew Yeoh, Nitin K. Ingle, Arvind Sundarrajan, Guan Huei See, Martinus Maria Berkens, Sameer A. Deshpande, Balasubramanian Pranatharthiharan, Yen-Chu Yang
  • Publication number: 20230064183
    Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.
    Type: Application
    Filed: August 29, 2022
    Publication date: March 2, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Suketu Arun Parikh, Ashish Pal, El Mehdi Bazizi, Andrew Yeoh, Nitin K. Ingle, Arvind Sundarrajan, Guan Huei See, Martinus Maria Berkens, Sameer A. Deshpande, Balasubramanian Pranatharthiharan, Yen-Chu Yang
  • Publication number: 20230056280
    Abstract: Exemplary methods of semiconductor processing may include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma of the carbon-containing precursor and the hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C. The methods may include halting flow of the carbon-containing precursor while maintaining the plasma with the hydrogen-containing precursor.
    Type: Application
    Filed: October 27, 2022
    Publication date: February 23, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Jialiang Wang, Susmit Singha Roy, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 11587930
    Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: February 21, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Nitin K. Ingle, Sung-Kwan Kang
  • Publication number: 20230035288
    Abstract: Methods open etch stop layers in an integrated environment along with metallization processes. In some embodiments, a method for opening an etch stop layer (ESL) prior to metallization may include etching the ESL with an anisotropic process using direct plasma to form helium ions that are configured to roughen the ESL for a first duration of approximately 10 seconds to approximately 30 seconds, forming aluminum fluoride on the ESL using remote plasma and nitrogen trifluoride gas for a second duration of approximately 10 seconds to approximately 30 seconds, and exposing the ESL to a gas mixture of boron trichloride, trimethylaluminum, and/or dimethylaluminum chloride at a temperature of approximately 100 degrees Celsius to approximately 350 degrees Celsius to remove aluminum fluoride from the ESL and a portion of a material of the ESL for a third duration of approximately 30 seconds to approximately 60 seconds.
    Type: Application
    Filed: July 6, 2022
    Publication date: February 2, 2023
    Inventors: Suketu PARIKH, Andrew YEOH, Tom S. CHOI, Joung Joo LEE, Nitin K. INGLE
  • Publication number: 20230031381
    Abstract: In some embodiments, an integrated tool for opening an etch stop layer and performing metallization comprises a first chamber with a remote plasma source, a direct plasma source, and a thermal source configured to open the etch stop layer on a substrate, a second chamber of the integrated tool with dry etch processing configured to pre-clean surfaces exposed by opening the etch stop layer, a third chamber of the integrated tool configured to deposit a barrier layer on the substrate, a fourth chamber of the integrated tool configured to deposit a liner layer on the substrate, and at least one fifth chamber of the integrated tool configured to deposit metallization material on the substrate. The integrated tool may also include a vacuum transfer chamber.
    Type: Application
    Filed: July 6, 2022
    Publication date: February 2, 2023
    Inventors: Suketu PARIKH, Andrew YEOH, Tom S. CHOI, Joung Joo LEE, Nitin K. INGLE
  • Patent number: 11515163
    Abstract: Exemplary methods of semiconductor processing may include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma of the carbon-containing precursor and the hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C. The methods may include halting flow of the carbon-containing precursor while maintaining the plasma with the hydrogen-containing precursor.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Jialiang Wang, Susmit Singha Roy, Abhijit Basu Mallick, Nitin K. Ingle
  • Publication number: 20220341042
    Abstract: Embodiments of the present disclosure generally relate to a batch processing chamber that is adapted to simultaneously cure multiple substrates at one time. The batch processing chamber includes multiple processing sub-regions that are each independently temperature controlled. The batch processing chamber may include a first and a second sub-processing region that are each serviced by a substrate transport device external to the batch processing chamber. In addition, a slotted cover mounted on the loading opening of the batch curing chamber reduces the effect of ambient air entering the chamber during loading and unloading.
    Type: Application
    Filed: July 11, 2022
    Publication date: October 27, 2022
    Inventors: Adib KHAN, Shankar VENKATARAMAN, Jay D. PINSON, II, Jang-Gyoo YANG, Nitin K. INGLE, Qiwei LIANG
  • Publication number: 20220223409
    Abstract: Exemplary methods of semiconductor processing may include providing a boron-and-carbon-and-nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include generating a capacitively-coupled plasma of the boron-and-carbon-and-nitrogen-containing precursor. The methods may include forming a boron-and-carbon-and-nitrogen-containing layer on the substrate. The boron-and-carbon-and-nitrogen-containing layer may be characterized by a dielectric constant below or about 3.5.
    Type: Application
    Filed: January 8, 2021
    Publication date: July 14, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick, Nitin K. Ingle
  • Publication number: 20220216058
    Abstract: Exemplary methods of semiconductor processing may include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma of the carbon-containing precursor and the hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C. The methods may include halting flow of the carbon-containing precursor while maintaining the plasma with the hydrogen-containing precursor.
    Type: Application
    Filed: January 6, 2021
    Publication date: July 7, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Jialiang Wang, Susmit Singha Roy, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 11355354
    Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. The methods may include thermally reacting the silicon-containing precursor, the oxygen-containing precursor, and the carbon-containing precursor at a temperature below about 650° C. The methods may include forming a silicon-and-oxygen-and-carbon-containing layer on the substrate.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: June 7, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick, Nitin K. Ingle