Abstract: Exemplary methods and systems of semiconductor processing may include etching a portion of a silicon-containing material from a substrate disposed within a processing region of a semiconductor processing chamber. Methods may include forming a low quality oxide within one or more of the recesses, where the low quality oxide and a silicon-containing material each contain an exposed surface. Methods include contacting the low quality oxide and the high quality semiconductor material with a passivating agent selective to a surface defect of the low quality oxide. Methods include contacting the substrate with an etching agent and/or a cleaning agent, where the contacting with the cleaning agent removes the high quality semiconductor material at an equal or faster rate than the low quality oxide.

Abstract: Semiconductor processing systems and methods for increased etch selectivity and rate are provided. Methods include etching a target material of a semiconductor substrate by flowing one or more plasma precursors through a microwave applicator into a remote plasma region of a semiconductor processing chamber. Generating a remote plasma within the remote plasma region at a microwave frequency, where the generated remote plasma comprises a density of greater than 1×1010 per cm3, an ion energy of less than or about 50 eV, or a combination thereof. Flowing the plasma effluents into a processing region of the semiconductor processing chamber. The microwave applicator includes a resonator body and a plate, where the resonator body is formed from or coated with a first dielectric material and the plate is formed from or coated with a second dielectric material.

Abstract: Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A first layer of silicon-and-germanium-containing material, a second layer of silicon-and-germanium-containing material, and a layer of silicon-containing material may be disposed on the substrate. The methods may include contacting the substrate with the oxygen-containing precursor. The contacting may oxidize at least a portion of the second layer of silicon-and-germanium-containing material. The methods may include providing a first etchant precursor to the processing region and contacting the substrate with the first etchant precursor. The contacting may selectively etch the first layer of silicon-and-germanium-containing material. The methods may include providing a second etchant precursor to the processing region.

Abstract: Exemplary methods for a coating a component of a semiconductor processing system may include forming a nickel-containing alloy on an exposed surface the component of the semiconductor processing system. The methods may include forming plasma effluents of a fluorine-containing precursor. The methods may include contacting the nickel-containing alloy with the plasma effluents of the fluorine-containing precursor. The contacting may fluorinate a portion of the nickel-containing alloy to form a nickel-and-fluorine-containing material overlying the nickel-containing alloy.

Abstract: Methods of filling a feature on a semiconductor substrate may include performing a process to fill the feature on the semiconductor substrate by repeatedly performing first operations. First operations can include providing a silicon-containing precursor. First operations can include contacting the substrate with the silicon-containing precursor to form a silicon-containing material within the feature defined on the substrate. First operations can include purging the semiconductor processing chamber. First operations can include providing an oxygen-and-hydrogen-containing precursor. First operations can include contacting the substrate with the oxygen-and-hydrogen-containing precursor to form a silicon-and-oxygen-containing material within the feature defined on the substrate.

Abstract: Exemplary semiconductor processing methods may include providing a pre-treatment precursor to a processing region of a semiconductor processing chamber. A first layer of silicon-and-germanium-containing material and a second layer of silicon-and-germanium-containing material may be disposed on a substrate housed within the processing region. A native oxide may be present on the first layer and the second layer. The methods may include contacting the substrate with the pre-treatment precursor to remove the native oxide. The methods may include providing an oxygen-containing precursor to the processing region. The methods may include contacting the substrate with the oxygen-containing precursor to oxidize at least a portion of the second layer. The methods may include providing an etchant precursor to the processing region. The methods may include contacting the substrate with the etchant precursor to selectively etch the first layer of silicon-and-germanium-containing material.

Abstract: Embodiments of the present disclosure generally relate to a batch processing chamber that is adapted to simultaneously cure multiple substrates at one time. The batch processing chamber includes multiple processing sub-regions that are each independently temperature controlled. The batch processing chamber may include a first and a second sub-processing region that are each serviced by a substrate transport device external to the batch processing chamber. In addition, a slotted cover mounted on the loading opening of the batch curing chamber reduces the effect of ambient air entering the chamber during loading and unloading.

Abstract: Exemplary semiconductor processing methods may include providing a pre-treatment precursor to a processing a remote plasma system of a semiconductor processing chamber. The methods may include generating plasma effluents of the pre-treatment precursor in the remote plasma system. The methods may include flowing plasma effluents of the pre-treatment precursor to a processing region of the semiconductor processing chamber. A substrate including alternating layers of material may be disposed within the processing region. The alternating layers of material may include a silicon-and-germanium-containing material. The methods may include contacting the substrate with the plasma effluents of the pre-treatment precursor. The methods may include etching the silicon-and-germanium-containing material. The methods may include providing a post-treatment precursor to the processing region. The methods may include contacting the substrate with the post-treatment precursor.

Abstract: The present disclosure generally relates to methods for forming silicon nitride film layers on substrates. In an embodiment, the method includes positioning a substrate having at least one feature thereon in a process chamber, depositing a first silicon film layer on a non-silicon oxide surface of the substrate for a time duration of about 1 to about minutes, nitriding the first silicon film layer to form a first silicon nitride film layer on the substrate, selectively depositing a second silicon film layer on the first silicon nitride film layer, and nitriding the second silicon film layer to form a second silicon nitride film layer disposed directly on the first silicon nitride film layer.

Abstract: A semiconductor processing method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include an exposed region of silicon-and-oxygen-containing material. The substrate may include an exposed region of a liner material. The methods may include providing a hydrogen-containing precursor to the semiconductor processing region. The methods may include contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor. The methods may include selectively removing at least a portion of the exposed silicon-and-oxygen-containing material.

Abstract: Exemplary methods of semiconductor processing may include providing a boron-and-carbon-and-nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include generating a capacitively-coupled plasma of the boron-and-carbon-and-nitrogen-containing precursor. The methods may include forming a boron-and-carbon-and-nitrogen-containing layer on the substrate. The boron-and-carbon-and-nitrogen-containing layer may be characterized by a dielectric constant below or about 3.5.

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

Abstract: Examples of the present technology include semiconductor processing methods to form diffusion barriers for germanium in a semiconductor structure. The methods may include forming a semiconductor layer stack from pairs of Si-and-SiGe layers. The Si-and-SiGe layer pairs may be formed by forming a silicon layer, and then forming the germanium barrier layer of the silicon layer. In some embodiments, the germanium-barrier layer may be less than or about 20 ?. A silicon-germanium layer may be formed on the germanium-barrier layer to complete the formation of the Si-and-SiGe layer pair. In some embodiments, the silicon layer may be an amorphous silicon layer, and the SiGe layer may be characterized by greater than or about 5 atom % germanium. Examples of the present technology also include semiconductor structures that include a silicon-germanium layer, a germanium-barrier layer, and a silicon layer.

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

Abstract: Hydrogen free (low-H) silicon dioxide layers are disclosed. Some embodiments provide methods for forming low-H layers using hydrogen-free silicon precursors and hydrogen-free oxygen sources. Some embodiments provide methods for tuning the stress profile of low-H silicon dioxide films. Further, some embodiments of the disclosure provide oxide-nitride stacks which exhibit reduced stack bow after anneal.

Abstract: Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.

Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.

Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.