Patents by Inventor Nitin Kumar
Nitin Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11610466Abstract: A hierarchical early-warning system for landslide probability issues a first level warning based on measured rainfall amounts exceeding a determined threshold, a second level warning, after the first level warning, based additionally on measured soil moisture content measured at different levels, and Factor of safety derived from forecasted pore pressure (FPP) each exceeding a determined threshold, a third level warning, after the first and the second level warnings, based additionally on ground movement measurements compared to a determined threshold, and a fourth level warning after the first, second and third level warnings, based additionally on data from movement-based sensors including strain gauge data.Type: GrantFiled: October 25, 2021Date of Patent: March 21, 2023Inventors: Maneesha Vinodini Ramesh, Divya Pullarkatt, Hemalatha Thirugnanam, Nitin Kumar M., P. Venkat Rangan
-
Patent number: 11610356Abstract: A method for providing sign language is disclosed. The method includes receiving, by an electronic device, a natural language information input from at least one source for conversion into sign language. The natural language information input includes at least one sentence. The method further includes predicting, by the electronic device, an emphasis score for each word of the at least one sentence based on acoustic components. The method further includes rephrasing, by the electronic device, the at least one sentence based on the emphasis score of each of the words. The method further includes converting, by the electronic device, the at least one rephrased sentence into the sign language. The method further includes delivering, by the electronic device, the sign language.Type: GrantFiled: December 14, 2020Date of Patent: March 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Deepak Sharma, Kamya Jaiswal, Akshar Bhatnagar, Asif Anis, Nitin Tanwar, Pratush Kumar Srivastava, Sushant Vobbilisetty
-
Publication number: 20230078487Abstract: An intelligent task assistant program can identify tasks associated with a user over a reporting period based on an analysis of, and inferences drawn from, data associated with one or more personal information programs, such as an electronic calendar application, an electronic reminder application, an electronic collaborative application, and/or an electronic communication application. The task assistant may also prioritize the identified tasks based on content associated with the tasks. Some or all of the prioritized tasks can be provided to an output device for perception by the user.Type: ApplicationFiled: November 17, 2022Publication date: March 16, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Vipindeep VANGALA, Prabuddh JAISWAL, Nitin PANDE, Nishchay KUMAR, Sandeep KADIYALA, Sibabrata PALADHI, Raunak OBEROI
-
Patent number: 11599633Abstract: Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method can determine, from a gate level representation of a circuit in a layout on a die of an IC, a first set of paths through the circuit that process security related data during operation of the circuit, the circuit including a second set of paths that do not process security related data; and the method can further determine, in a simulation of power consumption in the first set of paths but not the second set of paths, power consumption values in the first set of paths to determine potential security leakage of the security related data in the circuit. The method can further determine, from the power consumption values, positions in the layout for inserting virtual probes on the die for use in measuring security metrics that indicate potential leakage of the security related data. The insertion of the virtual probes is relative to the actual simulated layout of the die.Type: GrantFiled: February 12, 2021Date of Patent: March 7, 2023Assignee: ANSYS, INC.Inventors: Lang Lin, Norman Chang, Joao Geada, Deqi Zhu, Dinesh Kumar Selvakumaran, Nitin Kumar Pundir
-
Patent number: 11595438Abstract: Generally discussed herein are devices, systems, and methods for improving phishing webpage content detection. A method can include identifying first webpage content comprises phishing content, determining, using a reinforcement learning (RL) agent, at least one action, generating, based on the determined at least one action and the identified first webpage content, altered first webpage content, identifying that the altered first webpage content is benign, generating, based on the determined at least one action and second webpage content, altered second webpage content, and training, based on the altered second webpage content and a corresponding label of phishing, a phishing detector.Type: GrantFiled: April 29, 2021Date of Patent: February 28, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Eleanor Catherine Quint, Jugal Parikh, Mariusz Hieronim Jakubowski, Nitin Kumar Goel, Douglas J Hines, Cristian Craioveanu
-
Patent number: 11589243Abstract: Optimizing a performance of a software function withing a content distribution network, such as a software-implemented virtual cable modem termination system (CMTS) network, a virtualized Radio Access Network (vRAN), a Passive Optical Network (PON), or a Wi-Fi network. The performance may be optimized by dynamically changing a deployment location within the content distribution network for the software function from an original location to an updated location using an instance management platform. The deployment location may be dynamically changing in response to a variety of trigger conditions or concerns, such as but not limited to a difference in compute resources, responding to latency needs or tolerances, and a desired cohabitation of data or other software.Type: GrantFiled: May 10, 2021Date of Patent: February 21, 2023Assignee: Harmonic, Inc.Inventors: Nitin Kumar, Andrii Vladyka, Ihor Kopieichyk, Arkady Gilinsky, Pavlo Shcherbyna
-
Publication number: 20230046111Abstract: A hierarchical early-warning system for landslide probability issues a first level warning based on measured rainfall amounts exceeding a determined threshold, a second level warning, after the first level warning, based additionally on measured soil moisture content measured at different levels, and Factor of safety derived from forecasted pore pressure (FPP) each exceeding a determined threshold, a third level warning, after the first and the second level warnings, based additionally on ground movement measurements compared to a determined threshold, and a fourth level warning after the first, second and third level warnings, based additionally on data from movement-based sensors including strain gauge data.Type: ApplicationFiled: October 25, 2021Publication date: February 16, 2023Applicant: Amrita Vishwa VidyapeethamInventors: Maneesha Vinodini Ramesh, Divya Pullarkatt, Hemalatha Thirugnanam, Nitin Kumar M., P. Venkat Rangan
-
Publication number: 20230047451Abstract: Aspects of the present disclosure relate generally to isolator devices, components thereof, and methods associated therewith for substrate processing chambers. In one implementation, a substrate processing chamber includes an isolator ring disposed between a pedestal and a pumping liner. The isolator ring includes a first surface that faces the pedestal, the first surface being disposed at a gap from an outer circumferential surface of the pedestal. The isolator ring also includes a second surface that faces the pumping liner and a protrusion that protrudes from the first surface of the isolator ring and towards the outer circumferential surface of the pedestal. The protrusion defines a necked portion of the gap between the pedestal and the isolator ring.Type: ApplicationFiled: October 26, 2022Publication date: February 16, 2023Inventors: Nitin PATHAK, Amit Kumar BANSAL, Tuan Anh NGUYEN, Thomas RUBIO, Badri N. RAMAMURTHI, Juan Carlos ROCHA-ALVAREZ
-
Patent number: 11573842Abstract: Techniques for determining reliability of a workload migration activity are disclosed. In one embodiment, sub-tasks associated with the workload migration activity may be determined. Further, statistical data associated with an execution of the sub-tasks corresponding to different instances of the workload migration activity may be retrieved. Furthermore, a reliability model may be trained through machine learning using the statistical data to determine reliability of the workload migration activity. Then, the reliability of a new workload migration activity may be determined using the trained reliability model.Type: GrantFiled: April 9, 2021Date of Patent: February 7, 2023Assignee: VMWARE, INC.Inventors: Pramod Kumar P, Keerthi B Kumar, Nitin Madhusudan Agrawal, Shubham Shashikant Patil
-
Patent number: 11568976Abstract: Certain aspects of the present disclosure provide techniques for wound management and treatment. This includes determining characteristics of a wound for a patient based on an image of the wound, including detecting the characteristics based on analyzing the image using a first ML model trained to detect wound characteristics from a captured image. The techniques further include identifying patient medical data including characteristics relating to a medical history for the patient, and predicting a first care plan for the patient based on providing the characteristics of the wound and the patient medical data to a second ML model. The second ML model is trained to predict the first care plan using prior wound care outcome data including a prior wound care outcomes relating to prior patients. The first care plan is configured to be used to treat the wound for the patient.Type: GrantFiled: December 27, 2021Date of Patent: January 31, 2023Assignee: MatrixCare, Inc.Inventors: Jessica Rockne, Vivek Kumar, Adhiraj Ganpat Prajapati, Robert Price, Kedar Mangesh Kadam, Timothy James Heeren, Nitin Gandhi, Coleen Patrice Danielson
-
Publication number: 20230028391Abstract: Techniques for efficiently managing a file clone from a filesystem which supports efficient volume snapshots are provided. In some embodiments, a system may receive an instruction to remove the file clone from the filesystem. The file clone may be a point-in-time copy of metadata of an original file. The system may further—for a file map entry in a filesystem tree associated with the file clone, the file map entry indicating a data block—decrement a reference count in a reference count entry associated with the file map entry. The reference count entry may be stored in the filesystem tree according to a key and the key may comprise an identification of the original file. The system may further reclaim the data block in a storage system when the reference count is zero.Type: ApplicationFiled: October 4, 2022Publication date: January 26, 2023Inventors: Sriram Patil, Abhay Kumar Jain, Wenguang Wang, Nitin Rastogi, Pranay Singh, Richard P. Spillane
-
Publication number: 20230012567Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.Type: ApplicationFiled: June 21, 2022Publication date: January 19, 2023Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
-
Publication number: 20230012782Abstract: The present invention relates to a compound formula (I) and a process for preparing the same, wherein, R2, A, E, Hy, Ra, n, Q and W1 are each as defined in the description. The invention also relates to the combination and composition comprising the compound of formula (I).Type: ApplicationFiled: November 10, 2020Publication date: January 19, 2023Applicant: PI INDUSTRIES LTD.Inventors: Gajanan SHANBHAG, Singaraboena PRABHAKAR, Aditya SHARMA, Dipankar ROY, Mohan Lal MEHTA, Nitin Shivanna KORE, Mohan Kumar Shivani PUTTASWAMY, Santosh Shridhar AUTKAR, Ruchi GARG, Vishwanath GADE, Alexander G.M. KLAUSENER
-
Publication number: 20230013946Abstract: A self-regulating heater may comprise a first substrate including a first silicone layer and a first polyimide layer. A positive temperature coefficient heating element may be formed over the first polyimide layer. A second substrate may be located over the positive temperature coefficient heating element. The second substrate may include a second silicone layer and a second polyimide layer.Type: ApplicationFiled: May 2, 2022Publication date: January 19, 2023Applicant: B/E Aerospace, Inc.Inventors: Manjunath Hiremath, Rhushikesh Patil, Gururaja Bambila, Nitin Kumar Bagewadi
-
Publication number: 20230008833Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.Type: ApplicationFiled: June 27, 2022Publication date: January 12, 2023Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
-
Publication number: 20230012303Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.Type: ApplicationFiled: June 29, 2022Publication date: January 12, 2023Applicant: STMicroelectronics International N.V.Inventors: Kedar Janardan DHORI, Harsh RAWAT, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
-
Publication number: 20230008275Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Each row includes a word line drive circuit powered by an adaptive supply voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit generates the adaptive supply voltage for powering the word line drive circuits during the simultaneous actuation. A level of the adaptive supply voltage is modulated dependent on integrated circuit process and/or temperature conditions in order to optimize word line underdrive performance and inhibit unwanted memory cell data flip.Type: ApplicationFiled: June 20, 2022Publication date: January 12, 2023Applicant: STMicroelectronics International N.V.Inventors: Kedar Janardan DHORI, Nitin CHAWLA, Promod KUMAR, Manuj AYODHYAWASI, Harsh RAWAT
-
Publication number: 20230009329Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.Type: ApplicationFiled: June 27, 2022Publication date: January 12, 2023Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
-
Patent number: 11551391Abstract: Digital image dynamic shadow generation is described as implemented by a dynamic shadow system using one or more computing devices. The dynamic shadow system is configured to generate shadow objects based on one or more source objects included in a digital image (e.g., a two-dimensional digital image), automatically and without user intervention. The shadow object is based on a shape of the source object that is to “cast” the shadow and thus promotes realism. The shadow object is also generated by the dynamic shadow system to address an environment, in which, the shadow object is disposed within the digital image.Type: GrantFiled: February 15, 2021Date of Patent: January 10, 2023Assignee: Adobe Inc.Inventors: Rakesh Baidya, Praveen Kumar Dhanuka, Nitin Sharma, Arushi Jain
-
Patent number: 11544566Abstract: A method, computer system, and a computer program product for generating deep learning model insights using provenance data is provided. Embodiments of the present invention may include collecting provenance data. Embodiments of the present invention may include generating model insights based on the collected provenance data. Embodiments of the present invention may include generating a training model based on the generated model insights. Embodiments of the present invention may include reducing the training model size. Embodiments of the present invention may include creating a final trained model.Type: GrantFiled: June 3, 2019Date of Patent: January 3, 2023Assignee: International Business Machines CorporationInventors: Nitin Gupta, Himanshu Gupta, Rajmohan Chandrahasan, Sameep Mehta, Pranay Kumar Lohia