Abstract: Computer-implemented systems and methods for providing contextual game guidance are described herein. An example method includes determining based on contextual information regarding an application an objective of the user; automatically deriving based on the contextual information and the objective contextual guidance to assist the user; generating a user interface having the contextual guidance; and transmitting the user interface to a client device.

Abstract: A system for performing a failure assessment of an IC may comprise a hardware subsystem and a control subsystem to control operations performed by the hardware subsystem. The hardware system may change a duration of cycles of a clocking signal on the IC, and stop the clocking signal at a selected clock cycle. The operations may comprise changing the duration of selected clock cycles across a block of clock cycles, and performing a binary search across the block of clock cycles, such that the selected clock cycles are temporally placed at selected different locations within the block of clock cycles. At each iteration of the binary search, the system determines when a failure occurs. When the binary search indicates a single clock cycle causing a failure, the system stops clocking transitions at the single clock cycle, and the system extracts data from one or more circuit components of the IC.

Abstract: In an embodiment, a method includes initializing an input clock rotating register by sending a reset signal synchronized to an input clock signal and initializing an output clock rotating register by sending the reset signal synchronized to an output clock signal. The method further providing a data input synchronized to the output clock to a plurality of mux-flops. The output clock rotating register activates one of the plurality of mux-flops to receive the data input. The method further includes forwarding the data input via the one of the plurality of mux-flops to a multiplexer. The multiplexer has a selection input of the input clock rotating register. The method further includes selecting the data input as the output of the multiplexer to be a data output signal, such that the data output is synchronized with the input clock.

Abstract: A delay-locked loop (DLL) and corresponding method improve frequency of a chip. The DLL comprises a first programmable delay element configured to output a first clock, a second programmable delay element configured to output a second clock a phase detector. The phase detector includes a first clock input and a second clock input. The first and second programmable delay elements are further configured, in combination, to introduce a controllable skew between the first and second clocks. The DLL is configured to input the first and second clocks to the first and second clock inputs of the phase detector, respectively. The controllable skew is configured to improve the frequency of the chip.

Abstract: Computer-implemented systems and methods for providing contextual game guidance are described herein. An example method includes determining based on contextual information regarding an application an objective of the user; automatically deriving based on the contextual information and the objective contextual guidance to assist the user; generating a user interface having the contextual guidance; and transmitting the user interface to a client device.

Abstract: In an embodiment, a method includes filtering, with a low-pass filter, a voltage signal (Vdd) of a chip to create a filtered signal (Vref). The method further includes dividing Vref by a given factor. The method further includes determining whether a voltage droop occurred in Vdd by comparing Vdd to the divided Vref. The method further includes outputting a droop detection signal if Vdd is less than the divided Vref. In an embodiment, dividing Vref by the given factor includes selecting, with a multiplexer, one of a plurality of divided Vref signals outputted by a voltage divider. The selecting is based on a selection signal.

Abstract: Computer-implemented systems and methods for providing contextual game guidance are described herein. An example method includes determining based on contextual information regarding an application an objective of the user; automatically deriving based on the contextual information and the objective contextual guidance to assist the user; generating a user interface having the contextual guidance; and transmitting the user interface to a client device.

Abstract: Computer implemented methods and systems for providing a uniform data platform for at least one application of a plurality of applications are disclosed. Exemplary methods include receiving application data from at least one of a device and a server, a device executing a portion of an application of a plurality of applications, storing the application data in a data platform, the data model including at least one metadata and at least one event, the one metadata corresponding to at least one object indicated in the data model, and the one event corresponding to a trigger condition associated with the one metadata entry, wherein values of the one metadata and one event are associated with a user profile and accessing via a plurality of remote networked services, the application data stored in the data platform, the plurality of remote network services accessing the application data using the data model.

Abstract: A vulcanization mix includes: a) at least one elastomer; b) at least one cross-linking agent; and c) at least one polyol-based accelerator. A vulcanized elastomer can be obtained from the vulcanization mix. A process of preparation of the vulcanization mix and the vulcanized elastomer is also provided.

Abstract: A circuit and corresponding method for dynamic voltage frequency scaling (DVFS) on a chip employ a delay-locked loop (DLL)-based clocking architecture. The circuit comprises a DLL including a fixed delay line path, with a first insertion delay, and variable delay line path, with a second insertion delay, and a clock generator. The clock generator is configured to source a DLL input clock to the fixed and variable delay line paths at a start-up frequency prior to a run-time frequency. The start-up frequency is lower relative to a target frequency for the chip. The run-time frequency is configured based on DVFS, following release of the chip from reset. The chip is configured to be released from reset with the DLL locked at the start-up frequency, enabling the second insertion delay to match the first insertion delay with the DLL locked at the start-up frequency.

Abstract: An electronic processing system, and a method of operation thereof, including: a source module for providing a voting content of a game for utilizing a content voting feature in a social gaming network; a vote module, coupled to the source module, for generating votes for the game based on the voting content by selecting a game title of the game in a voting timeframe during a development of the game, the votes generated for exclusive memberships; and a result module, coupled to the vote module, for generating a voting result based on the votes in the voting timeframe for displaying on a screen.

Abstract: Computer-implemented systems and methods for providing contextual game guidance are described herein. An example method includes determining based on contextual information regarding an application an objective of the user; automatically deriving based on the contextual information and the objective contextual guidance to assist the user; generating a user interface having the contextual guidance; and transmitting the user interface to a client device.

Abstract: Computer implemented methods and systems for providing a uniform data platform for at least one application of a plurality of applications are disclosed. Exemplary methods include receiving application data from at least one of a device and a server, a device executing a portion of an application of a plurality of applications, storing the application data in a data platform, the data model including at least one metadata and at least one event, the one metadata corresponding to at least one object indicated in the data model, and the one event corresponding to a trigger condition associated with the one metadata entry, wherein values of the one metadata and one event are associated with a user profile and accessing via a plurality of remote networked services, the application data stored in the data platform, the plurality of remote network services accessing the application data using the data model.

Abstract: A circuit and corresponding method enable glitch-free frequency. The circuit comprises a first delay circuit and a second delay circuit, configured to produce first and second propagated enables, respectively, from first and second input enables, respectively; and an output clock circuit. The output clock circuit is configured to produce an output clock that switches, glitch-free, between a first phase-locked clock and a second phase-locked. The first and second delay circuits are further configured to enable the output clock to be switched, glitch-free, by employing the second propagated enable to gate propagation of the first input enable and the first propagated enable to gate propagation of the second input enable, respectively. The first and second input enables are configured to be enabled, alternately, causing the output clock to switch between the first and second phase-locked clocks.

Abstract: An improved shifter design for high-speed data processors is described. The shifter may include a first stage, in which the input bits are shifted by increments of N bits where N>1, followed by a second stage, in which all bits are shifted by a residual amount. A pre-shift may be removed from an input to the shifter and replaced by a shift adder at the second stage to further increase the speed of the shifter.

Abstract: Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge-rates at their input and small edge-rates at their output. Unbalanced circuit elements may be analyzed using a modified loaded ring oscillator. A statistical model and a fixed-corner model may be used to calculate timing delays associated with the unbalanced circuit elements and a timing delay error between the two models. The timing delay error may then be used to correct timing delays computed by static-timing models for similar unbalanced circuit elements within a more complex digital circuit.

Abstract: The present disclosure relates to an add and decode hardware logic circuit for adding two n bit inputs, A and B. A series of n logic stages are each configured to perform a first operation of propagating a result of a preceding stage on the condition that the sum of A[m] and B[m] is equal to 0, wherein 0<=m<n, perform a second operation of performing a bitwise left shift by 2m of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 1, or perform a third operation of performing a bitwise left shift by 2m+1 of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 2. An output at the last stage provides a decoded sum of the inputs A and B.

Abstract: An electronic processing system, and a method of operation thereof, including: a source module for providing a voting content of a game for utilizing a content voting feature in a social gaming network; a vote module, coupled to the source module, for generating votes for the game based on the voting content by selecting a game title of the game in a voting timeframe during a development of the game, the votes generated for exclusive memberships; and a result module, coupled to the vote module, for generating a voting result based on the votes in the voting timeframe for displaying on a screen.

Abstract: Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge-rates at their input and small edge-rates at their output. Unbalanced circuit elements may be analyzed using a modified loaded ring oscillator. A statistical model and a fixed-corner model may be used to calculate timing delays associated with the unbalanced circuit elements and a timing delay error between the two models. The timing delay error may then be used to correct timing delays computed by static-timing models for similar unbalanced circuit elements within a more complex digital circuit.

Abstract: An improved shifter design for high-speed data processors is described. The shifter may include a first stage, in which the input bits are shifted by increments of N bits where N>1, followed by a second stage, in which all bits are shifted by a residual amount. A pre-shift may be removed from an input to the shifter and replaced by a shift adder at the second stage to further increase the speed of the shifter.