Abstract: The present disclosure relates to an add and decode hardware logic circuit for adding two n bit inputs, A and B. A series of n logic stages are each configured to perform a first operation of propagating a result of a preceding stage on the condition that the sum of A[m] and B[m] is equal to 0, wherein 0<=m<n, perform a second operation of performing a bitwise left shift by 2m of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 1, or perform a third operation of performing a bitwise left shift by 2m+1 of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 2. An output at the last stage provides a decoded sum of the inputs A and B.

Abstract: In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch.

Abstract: In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch.

Abstract: The present disclosure includes, among other things, systems, methods and program products for pre-computing image manipulations.

Abstract: Integrated multiplexer/de-multiplexer for a pixel array is provided. A drive circuit having the de-multiplexer is provided to a gate line arranged for a pixel array. A pixel is selected using the drive circuit. A read circuit having the multiplexer is provided to a data line arranged for the pixel array. Data output from a pixel is read using the read circuit.

Abstract: The present disclosure includes, among other things, systems, methods and program products for pre-computing image manipulations.

Abstract: This invention presents Vt-shift invariant integrated multiplexer and de-multiplexer circuits that can be fabricated with a-Si:H, poly-crystalline silicon, or organic/polymer TFTs. The de-multiplexer and multiplexer includes a plurality of TFTs which are connected in series, and a drive TFT. These circuits are used with active matrix displays to control the gate addressing, and with imaging arrays to multiplex the read-out data.