Patents by Inventor Nitin Prasad
Nitin Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955355Abstract: A method and apparatus for substrate processing and a cluster tool including a transfer chamber assembly and a plurality of processing assemblies. Processing chamber volumes are sealed from the transfer chamber volume using a support chuck on which a substrate is disposed. A seal ring assembly is coupled to the support chuck. The seal ring assembly includes an inner assembly, an assembly bellows circumscribing the inner assembly, and a bellows disposed between the inner and outer platform. An inner ring is disposed between inner assembly of the seal ring assembly and the bottom surface of the support chuck. An outer ring disposed between the seal ring assembly and the lower sealing surface of the process chamber wall. The support chuck is raised to form an isolation seal between the processing chamber volume and the transfer chamber volume using the bellows, the inner ring, and the outer ring.Type: GrantFiled: February 25, 2021Date of Patent: April 9, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Kirankumar Neelasandra Savandaiah, Nitin Bharadwaj Satyavolu, Srinivasa Rao Yedla, Bhaskar Prasad, Thomas Brezoczky
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Patent number: 11949597Abstract: In an example method, an instruction to begin monitoring incoming traffic of a multicast data flow is received by a router. The instruction is received from a downstream router. The example method further includes monitoring incoming traffic of the multicast data flow. At least partly in response to determining that an expected amount of the incoming traffic of the multicast data flow is being received at the router, reporting to a network administrator device, a location of the router in the multicast data flow. Further, at least partly in response to determining that an expected amount of the incoming traffic of the multicast a data flow is not being received, sending, by the router and to an upstream router, an instruction to begin monitoring incoming traffic of the multicast data flow.Type: GrantFiled: December 6, 2021Date of Patent: April 2, 2024Assignee: Cisco Technology, Inc.Inventors: Mankamana Prasad Mishra, Anuj Budhiraja, Nitin Kumar, Sridhar Santhanam
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Patent number: 9274980Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: GrantFiled: April 7, 2014Date of Patent: March 1, 2016Assignee: Altera CorporationInventors: Renxin Xia, Juju Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Patent number: 9208357Abstract: Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.Type: GrantFiled: August 28, 2014Date of Patent: December 8, 2015Assignee: Altera CorporationInventors: Martin Langhammer, Juju Joyce, Keone Streicher, David Jefferson, Srinivas Reddy, Nitin Prasad
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Patent number: 9170775Abstract: A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.Type: GrantFiled: January 7, 2010Date of Patent: October 27, 2015Assignee: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Nitin Prasad, Greg Starr, Chiao Kai Hwang, Kumara Tharmalingam
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Patent number: 8826038Abstract: Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.Type: GrantFiled: May 18, 2012Date of Patent: September 2, 2014Assignee: Altera CorporationInventors: Martin Langhammer, Juju Joyce, Keone Streicher, David Jefferson, Srinivas Reddy, Nitin Prasad
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Publication number: 20140223034Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: ApplicationFiled: April 7, 2014Publication date: August 7, 2014Applicant: Altera CorporationInventors: Renxin Xia, Juju Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Patent number: 8719458Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: GrantFiled: September 12, 2013Date of Patent: May 6, 2014Assignee: Altera CorporationInventors: Renxin Xia, Juju Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Publication number: 20140015565Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: ApplicationFiled: September 12, 2013Publication date: January 16, 2014Applicant: ALTERA CORPORATIONInventors: Renxin Xia, Juju Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Patent number: 8615543Abstract: Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.Type: GrantFiled: June 22, 2011Date of Patent: December 24, 2013Assignee: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Steven Perry, Paul Metzgen, Nitin Prasad, William Hwang
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Patent number: 8554959Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: GrantFiled: May 1, 2012Date of Patent: October 8, 2013Assignee: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Publication number: 20120213017Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: ApplicationFiled: May 1, 2012Publication date: August 23, 2012Applicant: ALTERA CORPORATIONInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Patent number: 8209545Abstract: Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.Type: GrantFiled: May 21, 2010Date of Patent: June 26, 2012Assignee: Altera CorporationInventors: Martin Langhammer, Juju Joyce, Keone Streicher, David Jefferson, Srinivas Reddy, Nitin Prasad
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Patent number: 8190787Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: GrantFiled: December 3, 2009Date of Patent: May 29, 2012Assignee: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Patent number: 7991812Abstract: A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and/or arithmetically combining the outputs of multiple multipliers.Type: GrantFiled: September 21, 2009Date of Patent: August 2, 2011Assignee: Altera CorporationInventors: Martin Langhammer, Nitin Prasad
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Publication number: 20100169404Abstract: A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.Type: ApplicationFiled: January 7, 2010Publication date: July 1, 2010Inventors: Leon Zheng, Martin Langhammer, Nitin Prasad, Greg Starr, Chiao Kai Hwang, Kumara Tharmalingam
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Patent number: 7725738Abstract: Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.Type: GrantFiled: January 25, 2005Date of Patent: May 25, 2010Assignee: Altera CorporationInventors: Martin Langhammer, Juju Joyce, Keone Streicher, David Jefferson, Srinivas Reddy, Nitin Prasad
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Publication number: 20100082891Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: ApplicationFiled: December 3, 2009Publication date: April 1, 2010Applicant: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Patent number: 7660841Abstract: A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.Type: GrantFiled: February 20, 2004Date of Patent: February 9, 2010Assignee: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Nitin Prasad, Greg Starr, Chiao Kai Hwang, Kumara Tharmalingam
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Patent number: 7650438Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: GrantFiled: February 27, 2008Date of Patent: January 19, 2010Assignee: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel