Patents by Inventor Nitin Prasad
Nitin Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7650438Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: GrantFiled: February 27, 2008Date of Patent: January 19, 2010Assignee: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Publication number: 20100007379Abstract: A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and/or arithmetically combining the outputs of multiple multipliers.Type: ApplicationFiled: September 21, 2009Publication date: January 14, 2010Inventors: Martin Langhammer, Nitin Prasad
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Patent number: 7574533Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: GrantFiled: February 27, 2008Date of Patent: August 11, 2009Assignee: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Publication number: 20090100122Abstract: Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.Type: ApplicationFiled: November 26, 2008Publication date: April 16, 2009Applicant: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Steven Perry, Paul Metzgen, Nitin Prasad, William Hwang
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Patent number: 7467176Abstract: Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.Type: GrantFiled: February 20, 2004Date of Patent: December 16, 2008Assignee: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Steven Perry, Paul Metzgen, Nitin Prasad, William Hwang
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Publication number: 20080157813Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: ApplicationFiled: February 27, 2008Publication date: July 3, 2008Applicant: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Publication number: 20080143378Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: ApplicationFiled: February 27, 2008Publication date: June 19, 2008Applicant: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Patent number: 7356620Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: GrantFiled: June 10, 2003Date of Patent: April 8, 2008Assignee: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Publication number: 20060218216Abstract: A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and/or arithmetically combining the outputs of multiple multipliers.Type: ApplicationFiled: January 30, 2006Publication date: September 28, 2006Inventors: Martin Langhammer, Nitin Prasad
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Patent number: 7024446Abstract: A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and/or arithmetically combining the outputs of multiple multipliers.Type: GrantFiled: July 22, 2003Date of Patent: April 4, 2006Assignee: Altera CorporationInventors: Martin Langhammer, Nitin Prasad
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Publication number: 20060038586Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: ApplicationFiled: June 10, 2003Publication date: February 23, 2006Inventors: Renxin Xia, Juju Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Patent number: 6981206Abstract: A circuit for computing parity values is disclosed. The circuit includes a control decode unit. The control decode unit determines whether words received during a cycle correspond to more than one packet of data. The circuit includes a first parity processor. The first parity processor computes first parity sum values from first words associated with a first packet of data received during the cycle. The circuit includes a second parity processor. The second parity processor is capable of computing second parity sum values from second words associated with a second packet of data received during the cycle when the control decode unit determines that the data words correspond to more than one packet of data.Type: GrantFiled: December 10, 2002Date of Patent: December 27, 2005Assignee: Altera CorporationInventors: Ali Burney, Nitin Prasad
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Publication number: 20050187997Abstract: A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit. The least significant bits (LSBs) can be tied to ground and sent along the feedback path. To initialize the accumulator value, the MSBs of the initialization value can be input to the MAC block and sent directly to the add-subtract-accumulate unit. The LSBs can be sent to another multiplier that performs a multiply-by-one operation before being sent to the add-subtract-accumulate unit.Type: ApplicationFiled: February 20, 2004Publication date: August 25, 2005Inventors: Leon Zheng, Martin Langhammer, Nitin Prasad, Greg Starr, Chiao Hwang, Kumara Tharmalingam
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Publication number: 20050187999Abstract: Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.Type: ApplicationFiled: February 20, 2004Publication date: August 25, 2005Inventors: Leon Zheng, Martin Langhammer, Steven Perry, Paul Metzgen, Nitin Prasad, William Hwang
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Patent number: 6911923Abstract: Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.Type: GrantFiled: January 29, 2004Date of Patent: June 28, 2005Assignee: Altera CorporationInventors: Bonnie Wang, Chiakang Sung, Khai Nguyen, Joseph Huang, Gopi Rangan, Nitin Prasad
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Patent number: 6707399Abstract: Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.Type: GrantFiled: October 10, 2002Date of Patent: March 16, 2004Assignee: Altera CorporationInventors: Bonnie Wang, Chiakang Sung, Khai Nguyen, Joseph Huang, Gopi Rangan, Nitin Prasad
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Publication number: 20040015528Abstract: A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB.Type: ApplicationFiled: July 22, 2003Publication date: January 22, 2004Applicant: Altera CorporationInventors: Martin Langhammer, Nitin Prasad
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Patent number: 6628140Abstract: A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB.Type: GrantFiled: August 7, 2001Date of Patent: September 30, 2003Assignee: Altera CorporationInventors: Martin Langhammer, Nitin Prasad
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Patent number: 6625796Abstract: A method of configuring a set of programmable logic devices includes the step of partitioning a programming file into a set of programmable logic device configurations. A set of programmable logic devices are subsequently configured, in parallel, in accordance with the set of programmable logic device configurations.Type: GrantFiled: August 30, 2000Date of Patent: September 23, 2003Assignee: Altera CorporationInventors: Krishna Rangasayee, Nitin Prasad
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Publication number: 20030141898Abstract: A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB.Type: ApplicationFiled: August 7, 2001Publication date: July 31, 2003Applicant: Altera CorporationInventors: Martin Langhammer, Nitin Prasad