Abstract: A dynamic pipeline depth control method and apparatus is used with a bus which supports pipelined bus transactions. An agent coupled to the bus includes both a transmitter and a receiver. The transmitter is used to transmit an indication to the other agents coupled to the bus which prevents the other agents from issuing a transaction on the bus. The receiver is used to receive the indication, from another agent, that prevents the agent from issuing a transaction on the bus.

Abstract: Atomicity of lock variables is preserved in a computer system in response to a request by a microprocessor for a bus lock access whether the lock variable is split between two cache lines or is within a single cache line. A non-split lock bus access which can be satisfied by a cacheable region within the same cluster as the microprocessor issuing the access is allowed to complete, regardless of whether ownership of the next level bus is available. If the non-split lock access can not be satisfied within the cluster, then ownership of the next level bus is obtained, if available, to satisfy the access. Similarly, a split lock access may complete if ownership of the second level bus can be obtained. However, a split lock access is aborted if the second level bus ownership is not available, regardless of whether a cacheable region within the same cluster can satisfy the request.

Abstract: A method and apparatus for determining the timing of snoop windows in a pipelined bus includes a snoop timer, a snoop counter, and snoop resolution logic. The snoop timer indicates the number of clocks until the next snoop window. The snoop counter keeps track of the number of snoop windows currently being tracked by the apparatus and is updated by the snoop resolution logic. In one embodiment, the snoop resolution logic updates the snoop counter when a snoop event occurs on the bus. In one embodiment, the apparatus also includes snoop drive logic which drives snoop result signals onto the bus during snoop windows.

Abstract: In a computer system having a plurality of processors, an apparatus and method for maintaining processor ordering associated with read and write operations of these processors. When data from a producer processor is initially retired, it is stored in a FIFO buffer internal to that processor. If that processor subsequently wishes access to that data, the data is retrieved from and stored back to the FIFO. The data temporarily stored in the FIFO is used to update a main memory shared by the plurality of processors. This update function occurs only after the data has been globally observed in order to guarantee that if any other processor in the system reads data from the main memory, it will obtain an updated version of that data. This ensures that the processor ordering is maintained with respect to the multiple processors residing within the computer system.

Abstract: A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache.

Abstract: A method and apparatus for transferring information between a processor and a memory system utilizing a chunk write buffer, where read and write requests to the L2 cache memory are controlled by the processor. The cache line associated with each such request is larger than the interface coupling the L2 cache memory and the processor. Read requests are returned from the L2 cache memory to the processor in burst fashion. Write requests are transferred from the processor to the L2 cache memory during clock cycles in which the processor does not require the interface for a read request. Write requests need not be transferred in burst fashion; rather, a portion of the write request corresponding to the size of the interface, referred to as a chunk, is transferred from the processor to the L2 cache memory and stored temporarily in the chunk write buffer.

Abstract: A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.

Abstract: A microprocessor having a bus for the transmission of data, an execution unit for processing data and instructions, a memory for storing data and instructions, and a write combining buffer for combining data of at least two write commands into a single data set, wherein the combined data set is transmitted over the bus in one clock cycle rather than two or more clock cycles. Thereby, buss traffic is minimized. The write combining buffer is comprised of a single line having a 32-byte data portion, a tag portion, and a validity portion. The tag entry specifies the address corresponding to the data currently stored in the data portion. There is one valid bit corresponding to each byte of the data portion which specifies whether that byte currently contains useful data. So long as subsequent write operations to the write combining buffer result in hits, the data is written to the buffer's data portion. But when a miss occurs, the line is reallocated, and the old data is written to the main memory.

Abstract: A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.

Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

Abstract: A system and method for providing a high performance symmetric arbitration protocol that includes support for priority agents. The bus arbitration protocol supports two classes of bus agents: symmetric agents and priority agents. The symmetric agents support fair, distributed arbitration using a round-robin algorithm. Each symmetric agent has a unique Agent ID assigned at reset. The algorithm arranges the symmetric agents in a circular order of priority. Each symmetric agent also maintains a bus ownership state of busy or idle and a Rotating ID that reflects the symmetric agent with the lowest priority in the next arbitration event. On an arbitration event, the symmetric agent with the highest priority becomes the symmetric owner. However, the symmetric owner is not necessarily the overall bus owner (i.e., a priority agent may be the overall bus owner).

Abstract: Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent.

Abstract: A protocol and related apparatus for snoop stretching in a computer system having at least one requesting agent for issuing bus transaction requests and at least one snooping agent for monitoring transaction requests and issuing bus signals onto an external bus. The bus transactions are timed by a bus clock signal having a plurality of cycles. To indicate snoop stretching, during a first cycle a first snooping agent asserts both a HIT# bus signal and a HITM# bus signal together to indicate that the first snooping agent must delay assertion of valid snoop results for a predetermined snoop period. During a later cycle, to indicate the end of the snoop stretch, the first snooping agent deasserts the assertion of both the HIT# and HITM# signals together and asserts its valid snoop results. The HIT# and HITM# signals alone each represent valid snoop results.

Abstract: A method and apparatus of performing bus transactions on the external bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

Abstract: A multiprocessor programmable interrupt controller system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt request (IRQ) related messages. Each processor chip has an on-board interrupt acceptance unit (IAU) coupled to the interrupt bus to accept IRQs and to broadcast IRQs that it generates. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus to broadcast I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two wires for data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to this procedure also provides uniform distribution of IRQs to eligible processors.

Abstract: In a multi-processor system having a first processor, a second processor, and a bus coupling the first processor to the second processor, a method for correcting an erroneous signal corresponding to the first processor while maintaining lock atomicity. When an erroneous transaction is detected, the first processor aborts that transaction and performs a retry. On the retry, an arbitration process arbitrates between the first processor and the second processor to determine which processor is granted access to the bus. If an error is detected during the arbitration process, an arbitration re-synchronization process is initiated. In the arbitration re-synchronization process, bus requests are de-asserted and then re-arbitrated. In the re-arbitration process, the first processor initiates its request ahead of the other processor in order to maintain lock atomicity.

Abstract: In a computer system having a plurality of processors with internal caches, a method for handling race conditions arising when multiple processors simultaneously write to a particular cache line. Initially, a determination is made as to whether the cache line is in an exclusive, modified, invalid, or shared state. If the cache line is in either the exclusive or modified state, the cache line is written to and then set to the modified state. If the cache line is in the invalid state, a Bus-Read-Invalidate operation is performed. However, if the cache line is in the shared state and multiple processors initiate Bus-Write-Invalidate operations, the invalidation request belonging to the first processor is allowed to complete. Thereupon, the cache line is sent to the exclusive state, data is updated, and the cache line is set to the modified state. The second processor receives a second cache line, updates this second cache line, and sets the second cache line to the modified state.

Abstract: A multiprocessor programmable interrupt controller system, for use in a multiprocessor system in which one processor unit is a functional redundant checking (FRC) unit, has a synchronous interrupt bus, distinct from the system (memory) bus, with an interrupt bus clock that has a frequency that is a subharmonic of the FRC unit master CPU clock, for handling interrupt request (IRQ) related messages and maintaining synchronism between the master and checker CPUs of the FRC unit. Additional embodiments provide for the use of D-type flip-flop synchronizers to accommodate FRC units whose internal (core) clock or external bus clock are not harmonically related to the interrupt clock frequency. Each processor unit has an interrupt acceptance unit (IAU) coupled to the interrupt bus for the acceptance of IRQs and for broadcasting of IRQs generated by its associated on-chip processor.