Patents by Inventor Noboru Kubo

Noboru Kubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6158046
    Abstract: A computer device includes a processor for processing an object code containing a plurality of instruction words. It further includes a memory for storing a plurality of pseudoinstruction words respectively corresponding to the plurality of instruction words. Preferably, the number of bits of each of the plurality of pseudoinstruction words is less than that of each of the plurality of instruction words. Finally, the computer device includes an instruction word converter for converting the pseudoinstruction word read out from the memory into an instruction word of the object code, and for outputting the instruction word obtained by the conversion to the processor.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: December 5, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yukihiro Yoshida, Kunihiro Katayama, Noboru Kubo
  • Patent number: 5619676
    Abstract: The high speed semiconductor memory includes at least one memory module and a cache controller. The at least one memory module includes a plurality of memory cells for storing data and a cache memory for storing part of the data stored in the plurality of memory cells, The cache controller includes a hit ratio counter for obtaining an average cache hit ratio and a comparator storing a desired threshold hit value and comparing the average cache hit ratio with the desired threshold value. The cache controller determines whether data corresponding to an input address are stored in the cache memory and allows to readout such data from the cache memory, otherwise controlling the read-out of data from the plurality of memory cells for storage in the cache memory so as to update the contents of the cache memory. A request signal for transferring data from the memory cells to the cache memory is generated when the average cache hit ratio is lower than the desired threshold value.
    Type: Grant
    Filed: July 2, 1996
    Date of Patent: April 8, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoyuki Fukuda, Yukihiro Yoshida, Noboru Kubo, Kazuo Kinosita
  • Patent number: 5367623
    Abstract: An information processing apparatus has a capability of opening two or more windows and processing an object such as text, graphics, and a picture on each page. This information processing unit includes a pasting unit for pasting a tag window at any location on each page, a registering unit for registering one or more objects in the tag window, and a linking unit for linking the page to the tag window or unlinking the tag window from the page.
    Type: Grant
    Filed: September 25, 1991
    Date of Patent: November 22, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiyuki Iwai, Kunihiko Iizuka, Yumi Yamauchi, Atsushi Aoki, Noboru Kubo
  • Patent number: 5345548
    Abstract: A character display apparatus with an attribute management unit for storing an attribute of a used font, a raster image storage unit for storing a raster image of the used font, and an image position management unit for storing a storage position of each raster image in the raster image storage unit in correspondence with each attribute of the attribute management unit. The character display apparatus also includes a judgment unit for judging whether a raster image of a character to be displayed is stored in the raster image storage unit or not, by referring to the attribute management unit and the image position management unit. The character display apparatus is further provided with a display unit for displaying an image of the character by use of the raster image in the raster image storage unit, in case that the raster image is stored therein.
    Type: Grant
    Filed: May 20, 1991
    Date of Patent: September 6, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tatsuya Nomura, Yumi Yamauchi, Kenji Mameda, Shigeru Yoshida, Noboru Kubo
  • Patent number: 5287443
    Abstract: An apparatus for editing documents input from an input device, capable of reducing a process time of renewing the documents to be displayed on a display device and capable of increasing a displaying speed of the renewed documents during an editing process includes a document storing unit for storing document data, a text-layout information storing unit for storing text-layout information separately in accordance with a preceding time and a succeeding time with respect to an editing operation, the text-layout information indicating positions of the document data on the display device at a time when the document data are displaying, a display image storing unit for storing image data, the image data being used for displaying the document data stored in the document storing unit on the display device in accordance with the text-layout information in the preceding time stored in the text-layout information storing unit, an editing unit for producing the text-layout information in the succeeding time from the text
    Type: Grant
    Filed: May 21, 1991
    Date of Patent: February 15, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenji Mameda, Shigeru Yoshida, Shuichiro Ono, Noboru Kubo
  • Patent number: 4574950
    Abstract: A wafer box having a variable wafer slot size including a wafer box body of a rectangular parallelpiped shape having parallel wafer inserting grooves formed in inner side surfaces thereof extending in a vertical direction, a plurality of parallel fixing plate inserting grooves formed in the end surfaces and extending in a vertical direction, and an open upper part. At least one fixing plate, also having a plurality of wafer receiving grooves formed on at least one surface thereof, is inserted into a selected pair of the fixing plate inserting grooves. Both ends of the plate are shaped so as to be easily insertable and removable. Buffer members are placed between the side surfaces in the upper and lower portions of the box to support the wafers from the upper and lower sides thereof. A closure covers the upper part of the box.
    Type: Grant
    Filed: April 20, 1984
    Date of Patent: March 11, 1986
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kiyohiko Koe, Jun Yamaguchi, Noboru Kubo, Hiroshi Matsumoto, Mamoru Sugimoto, Keiji Fukumura