Abstract: A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.

Abstract: A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.

Abstract: A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.

Abstract: A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.

Abstract: An integrated circuit (“IC”) package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.

Abstract: A optoelectronic package includes an inner package with a dielectric substrate having at least a first dielectric level with a photodetector (PD) die on a die attach area, first routing connecting a first contact to a first external bond pad (FEBP), and second routing connecting a second contact to a second external bond pad (SEBP). An outer package (OP) includes a ceramic substrate including a light source die on a base portion in direct line of sight with the PD including a first electrode and second electrode. A first wire bond connects the FEBP to a first terminal, a second wire bond connects the SEBP to a second terminal, a third wire bond connects the first electrode to a third terminal, and a fourth wire bond connects the second electrode to a fourth terminal.

Abstract: An integrated circuit (“IC”) package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.

Abstract: An integrated circuit (“IC”) package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.

Abstract: An integrated circuit (“IC”) package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.

Abstract: A liquid crystal display element (10) of the present invention includes a transparent common electrode (40) which is provided in a layer between (i) a scan line (20) and a signal line (19) and (ii) a pixel electrode (30) so that the transparent common electrode (40) covers a location which faces at least one of (i) at least part of the scan line (20) and (ii) at least part of the signal line (19), the transparent common electrode (40) having an opening part (41) at a location which faces the pixel electrode (30).

Abstract: A packaged device (100) with a semiconductor chip (101) with a MEMS device (102) in the central chip area, wherein the package includes a light-sensitive first (150) and an opaque second (160) polymerized compound. The second compound (160) encapsulates the chip peripheral areas with the terminals (103) and wire bonds (130), and forms a sidewall (160a, diameter 112) around the un-encapsulated central area. The first compound (150) continues from the sidewall inward as a frame (inner diameter 110) around the un-encapsulated central area.

Abstract: A optoelectronic package includes an inner package with a dielectric substrate having at least a first dielectric level with a photodetector (PD) die on a die attach area, first routing connecting a first contact to a first external bond pad (FEBP), and second routing connecting a second contact to a second external bond pad (SEBP). An outer package (OP) includes a ceramic substrate including a light source die on a base portion in direct line of sight with the PD including a first electrode and second electrode. A first wire bond connects the FEBP to a first terminal, a second wire bond connects the SEBP to a second terminal, a third wire bond connects the first electrode to a third terminal, and a fourth wire bond connects the second electrode to a fourth terminal.

Abstract: An active matrix substrate (100A) includes a thin film transistor (20), a scanning line (11) substantially parallel to a first direction, a signal line (12) substantially parallel to a second direction which is orthogonal to the first direction, a first interlayer insulating layer (16) covering the thin film transistor, a lower layer electrode (17) provided on the first interlayer insulating layer, a dielectric layer (18) provided on the lower layer electrode, and an upper layer electrode (19) overlapping at least a portion of the lower layer electrode via the dielectric layer. A first contact hole (31) for allowing the upper layer electrode to be electrically connected to a drain electrode (24) of the thin film transistor includes a first aperture (16a) formed in the first interlayer insulating layer and a second aperture (18a) formed in the dielectric layer.

Abstract: In a liquid crystal display device, a plurality of pixel electrodes respectively connected to a plurality of source bus lines are arranged along an extension direction of the source bus line, the pixel electrodes being alternately displaced to one side and then the other in an arrangement direction of the plurality of source bus lines. Thin film transistors each include a semiconductor layer containing a source portion, a channel portion and a drain portion, and a gate electrode formed using a portion of the gate bus line. The source portion, the channel portion and the drain portion are arranged so as to be adjacent to one another in a direction perpendicular to the arrangement direction of the plurality of source bus lines. The gate electrode extends in a direction parallel to the arrangement direction of the plurality of source bus lines and is arranged to oppose the channel portion.

Abstract: In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a dicing tape and an anchoring material. The anchoring material and the wafer are cut with the sawing blade. During the cutting operation, the anchoring material reduces backside chipping of the die and eliminates fly-away die. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.

Abstract: Arbitrary one pixel P (contact hole pixel (13)) is selected in a predetermined demarcated area (20) of the liquid crystal display device of the present invention. The pixel P is (i) any of four pixels Q1 through Q4 (contact hole pixels (13)) closest to another pixel P or (ii) (a) contained in a quadrangle whose vertices correspond to respective four pixels Q1 through Q4 closest to the pixel P and (b) any of four pixels Q1 through Q4 closest to another pixel P. Further, two diagonal lines of a quadrangle formed by four pixels Q1 through Q4 are inclined at respective two angles with respect to a gate bus line (line segment A-B), and a difference between the two angles is smaller than 30 degrees. Moreover, the contact hole pixels (13) are provided for respective source bus lines in the predetermined demarcated area (20).

Abstract: An active matrix substrate (100A) includes a thin film transistor (20), a scanning line (11) substantially parallel to a first direction, a signal line (12) substantially parallel to a second direction which is orthogonal to the first direction, a first interlayer insulating layer (16) covering the thin film transistor, a lower layer electrode (17) provided on the first interlayer insulating layer, a dielectric layer (18) provided on the lower layer electrode, and an upper layer electrode (19) overlapping at least a portion of the lower layer electrode via the dielectric layer. A first contact hole (31) for allowing the upper layer electrode to be electrically connected to a drain electrode (24) of the thin film transistor includes a first aperture (16a) formed in the first interlayer insulating layer and a second aperture (18a) formed in the dielectric layer.

Abstract: A liquid crystal display element (10) of the present invention includes a transparent common electrode (40) which is provided in a layer between (i) a scan line (20) and a signal line (19) and (ii) a pixel electrode (30) so that the transparent common electrode (40) covers a location which faces at least one of (i) at least part of the scan line (20) and (ii) at least part of the signal line (19), the transparent common electrode (40) having an opening part (41) at a location which faces the pixel electrode (30).

Abstract: A method of assembling semiconductor devices includes connecting a bond wire between a bond pad on a top side surface of a semiconductor die having its bottom side surface attached to a package substrate and a bonded area within a metal terminal of the package substrate, where a bond is formed along a bonding interface between the bond wire and bonded area. After the connecting, a metal paste is applied including a plurality of metal particles and a binder over the bonded area. The metal paste is sintered to densify the plurality of metal particles to form reinforcement material including within a portion of the bonding interface for providing improved wirebond performance, such as increased pull strength.

Abstract: Arbitrary one pixel P (contact hole pixel (13)) is selected in a predetermined demarcated area (20) of the liquid crystal display device of the present invention. The pixel P is (i) any of four pixels Q1 through Q4 (contact hole pixels (13)) closest to another pixel P or (ii) (a) contained in a quadrangle whose vertices correspond to respective four pixels Q1 through Q4 closest to the pixel P and (b) any of four pixels Q1 through Q4 closest to another pixel P. Further, two diagonal lines of a quadrangle formed by four pixels Q1 through Q4 are inclined at respective two angles with respect to a gate bus line (line segment A-B), and a difference between the two angles is smaller than 30 degrees. Moreover, the contact hole pixels (13) are provided for respective source bus lines in the predetermined demarcated area (20).