Abstract: A liquid crystal display is provided which has low power consumption, and which prevents horizontal stripes from occurring without the circuitry becoming more complex. When the write voltage polarity is inverted every plurality of lines, in the n line where the polarity is inverted, the rise in the drain line waveform dulls due to the charging of the drain line. In the n+1 line, because the drain line has been charged by the writing of the n line, waveform dullness does not occur. A difference between the write states in the two lines causes horizontal stripes. Consequently, the output enable signal is activated at the rise of the clock signal, and the gate line is activated after a predetermined time to start the writing. Therefore, writing is not performed during the period of waveform dullness, and the write state is the same across all scan lines.

Abstract: A driving circuit of a color liquid crystal display is provided which is capable of reducing a substrate packaging area and using a common substrate or TCP (Tape Carrier Package) even when a resolution and/or the number of gray scale voltages that the color liquid crystal display provides are different, which enables the substrate, TCP, and a display device to be fabricated at low costs. In the driving circuit of the color liquid crystal display, a data electrode driving circuit produces gray scale voltages corresponding to gray scale voltage characteristics based on serial data made up of gray scale information and gray scale voltage information.

Abstract: In a liquid crystal display device where each unit pixel p arranged on a liquid crystal panel 101A is constituted by a plurality of pixels p1, p2, and p3, the pixels p1, p2, and p3 are divided into sub-pixels p11 and p12, sub-pixels p21, and p22, and sub-pixels p31 and p32, respectively. The liquid crystal display device is provided with driver ICs 201 and 202 for driving the sub-pixels p11, p21, and p31, and the sub-pixels p12, p22, and p32 constituting the pixels so that different gradation-brightness value characteristics may be given. Due to this, multi-gradation display can be performed.

Abstract: A display panel 13 having a plurality of pixels 14 each divided into P (P=3) sub-pixels 15a, 15b and 15c, and a source driver 12 for driving each pixel 14 in accordance with three J (=8)-bit data values corresponding to the sub-pixels 15a, 15b, and 15c, and a signal processing circuit 12 for distributing K(=12)-bit (K>J) input image data as M (M=6) time-shared frame data values and supplying the frame data values to the source driver 12 are arranged. 2K−J (=16) gray levels insufficient due to the difference between the numbers of bits of K-bit input image data and J-bit driving signals of the source driver 12 is realized by combinations of time-shared frame data of (P×M=18) ways performed for the sub-pixels 15a, 15b, and 15c in accordance with the M time-shared frame data values.

Abstract: An active matrix-type liquid crystal display device which is capable of realizing a dot inversion driving by disposing H drivers on both sides of the liquid crystal panel, while using existing H driver circuits which output odd output data and even output data at opposite polarities to each other. The first and second H drivers, which output odd output data and even output data at opposite polarities to each other, are disposed facing each other on both sides of the liquid crystal panel, in order to realize an active matrix-type liquid crystal display device which is conducted by the dot inversion driving. Data electrodes of said liquid crystal display device are taken out for every two lines or every integer times of two lines and the thus taken out data lines are connected alternately to the first and second driver circuits.

Abstract: A liquid crystal display control circuit receives a data enable signal DE in synchronization with per-line based display data from a computer, and thereby controls a liquid crystal display. A gate drive signal outputted from a gate driver 23 is generated according to a vertical clock signal VCK in synchronization with a rise of the signal DE. In order to avoid a variation in the period of charging the pixel electrodes which is caused by a delay in the rise timing of the signal DE and a delay in the signal VCK after the last line, a gate enable signal generation circuit 10 is provided in the liquid crystal display control circuit 1, whereby the extended output of the pulse of the gate drive signal caused by the above-mentioned delays is inhibited. This avoids display inhomogeneity caused by a variation in the data enable signal and the like.

Abstract: A method of driving a display apparatus, includes (a) providing a plurality of processors outputting a plurality of output signals, respectively; (b) providing a plurality of frames, wherein each of the plurality of frames has an averaging pattern for averaging characteristic errors of the plurality of processors and has a plurality of lines; (c) performing a first scanning on a predetermined frame of the plurality of frames such that a predetermined line of the plurality of lines of the predetermined frame is not scanned; and (d) performing a second scanning on a specific frame of the plurality of frames such that a line corresponding to the predetermined line of the specific frame is scanned, the specific frame having a same averaging pattern as the averaging pattern of the predetermined frame.

Abstract: A liquid crystal display (LCD) panel unit is provided with a plurality of source drivers which are functionally divided into first and second source driver groups respectively assigned to first and second halves of an LCD panel. In order to properly drive the LCD panel irrespective of incoming pixel data of different formats, a pixel data rearrangement circuit is provided for rearranging the incoming pixel data to a predetermined data format. The data rearrangement circuit precedes the first and second source driver groups, and functions such as to receive 2N-path (N is a natural number) pixel data and rearranges the orders of the 2N-path pixel data according to the predetermined data format, and applies the rearranged N-path pixel data to the first source driver group and applying the rearranged other N-path pixel data to the second source driver group.

Abstract: There is provided an active matrix-type liquid crystal display device which is capable of realizing a dot inversion driving by disposing H drivers on both sides of the liquid crystal panel, while using existing H driver circuits which output odd output data and even output data at opposite polarities to each other.

Abstract: A driving circuit of a color liquid crystal display is provided which is capable of reducing a substrate packaging area and using a common substrate or TCP (Tape Carrier Package) even when a resolution and/or the number of gray scale voltages that the color liquid crystal display provides are different, which enables the substrate, TCP, and a display device to be fabricated at low costs. In the driving circuit of the color liquid crystal display, a data electrode driving circuit produces gray scale voltages corresponding to gray scale voltage characteristics based on serial data made up of gray scale information and gray scale voltage information.

Abstract: A liquid crystal display is provided which has low power consumption, and which prevents horizontal stripes from occurring without the circuitry becoming more complex. When the write voltage polarity is inverted every plurality of lines, in the n line where the polarity is inverted, the rise in the drain line waveform dulls due to the charging of the drain line. In the n+1 line, because the drain line has been charged by the writing of the n line, waveform dullness does not occur. A difference between the write states in the two lines causes horizontal stripes. Consequently, the output enable signal is activated at the rise of the clock signal, and the gate line is activated after a predetermined time to start the writing. Therefore, writing is not performed during the period of waveform dullness, and the write state is the same across all scan lines.