Abstract: [Object] Provided are a light receiving device and a light receiving circuit that are capable of performing highly accurate ranging with an increased field of view (FOV). [Solving Means] A light receiving device according to the present disclosure includes a light detector array including a plurality of pixels each configured to output a pulse in response to a reaction of a light detector with a photon, a counter circuit configured to count the pulse outputted from at least one of the pixels of the light detector array, and a control circuit configured to select, from the light detector array, one of the pixels to be enabled and one of the pixels to be disabled, on the basis of the number of counts of the pulse from the counter circuit.

Abstract: The present disclosure relates to a measurement device, a measurement method, and a program that enable measurement of a distance with high accuracy in a shorter time. A signal for giving an instruction on emission timing to emit a pulse of laser light is generated repeatedly for each predetermined processing cycle, and a count code indicating timing at which a pulse of reflected light that is the laser light reflected by a distance measurement target and returned is received is continuously counted at the time of switching a processing cycle. Then, an instruction on an emission delay value indicating a time for delaying the emission timing from the start of the processing cycle is given to be different for each processing cycle. The present disclosure can be applied to a measurement device that measures a distance.

Abstract: The present disclosure relates to a measurement device, a measurement method, and a program that enable measurement in a shorter time. A signal for giving an instruction on emission timing to emit a pulse of laser light is generated in order to output the laser light having the number of pulse emissions of two or more times within a distance measurement range time of one time by setting, as the distance measurement range time, a width of a flight time in which light reciprocates between the measurement device and a distance measurement range representing a fixed distance width including a distance to be measured.

Abstract: Provided is a programmable logic integrated circuit wherein even if a failure occurs in any resistance-variable element, remedy would be possible and hence the improvement of reliability has been achieved. In a programmable logic integrated circuit comprising resistance-variable elements, when the states of the resistance-variable elements are to be changed according to externally inputted configuration information, a control means uses a reading means to read the states of the respective resistance-variable elements, and then uses a writing means to change only the states of resistance-changing elements that are different from a state indicated by the configuration information.

Abstract: An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.

Abstract: In order to provide a technique for reducing an area of a content addressable memory cell and suppressing a leak current in a content addressable memory which calculates similarity, a content addressable memory cell of the present invention, comprising: a resistance network which includes plural current paths, a logic circuit for selecting a current path in response to input data, and a variable-resistance-type non-volatile memory element that is arranged on at least one current path and stores data and whose resistance value is changed according to a result of logical calculation based on the input data and the stored data; and a charge/discharge circuit which is connected with the resistance network and a match line and whose delay time from inputting a signal through the match line until outputting the signal is changed according to the result of logical calculation based on the input data and the stored data.

Abstract: An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.

Abstract: In order to provide a crossbar switch type memory circuit designed to be usable in normal circumstances even when a resistance change element is in an adverse state, the present invention is provided with: a first unit including a first column wiring to which one end of a first resistance change element is connected, a first power supply-side transistor for controlling the connection of the first column wiring and a power supply node, a first ground-side transistor, of a reverse operation type to the first power supply-side transistor, for controlling the connection of the first column wiring and a ground node, and a first polarity control line for causing the first power supply-side transistor or the first ground-side transistor to turn on and the other to turn off by a polar signal from a polar signal terminal, the first polarity control line being connected to the control terminals of the first power supply-side transistor and first ground-side transistor; a second unit including a second column wiring to

Abstract: A reconfigurable circuit comprising: a first level crossbar switch that has first non-volatile resistive switches; a second level crossbar switch that has second non-volatile resistive switches; and a first wire and third non-volatile resistive switches that are used for redundancy, wherein input wires of the second level crossbar switch are connected to output wires of the first level crossbar switch one-to-one, and input wires of the first level crossbar switch and output wires of the second level crossbar switch are connected to the first wire through the third non-volatile resistive switches.

Abstract: In order to stably write data into a magnetic memory that uses in-plane current-induced perpendicular switching of magnetization to write data, the magnetic memory includes a recording layer formed as a perpendicular magnetization film, an adjacent layer joined to an upper surface or a lower surface of the recording layer, an external magnetic field application part configured to apply a first external magnetic field to the recording layer in a first direction which is an in-plane direction of the recording layer, and a current application part configured to allow a write current to flow through the adjacent layer in the first direction or a second direction which is opposite to the first direction. The external magnetic field application part is configured to switch a direction of a second external magnetic field applied in a direction perpendicular to the first direction in accordance with a direction of the write current.

Abstract: Provided is a programmable logic integrated circuit wherein even if a failure occurs in any resistance-variable element, remedy would be possible and hence the improvement of reliability has been achieved. In a programmable logic integrated circuit comprising resistance-variable elements, when the states of the resistance-variable elements are to be changed according to externally inputted configuration information, a control means uses a reading means to read the states of the respective resistance-variable elements, and then uses a writing means to change only the states of resistance-changing elements that are different from a state indicated by the configuration information.

Abstract: A reconfigurable circuit comprising: a first level crossbar switch that has first non-volatile resistive switches; a second level crossbar switch that has second non-volatile resistive switches; and a first wire and third non-volatile resistive switches that are used for redundancy, wherein input wires of the second level crossbar switch are connected to output wires of the first level crossbar switch one-to-one, and input wires of the first level crossbar switch and output wires of the second level crossbar switch are connected to the first wire through the third non-volatile resistive switches.

Abstract: In order to provide a crossbar switch type memory circuit designed to be usable in normal circumstances even when a resistance change element is in an adverse state, the present invention is provided with: a first unit including a first column wiring to which one end of a first resistance change element is connected, a first power supply-side transistor for controlling the connection of the first column wiring and a power supply node, a first ground-side transistor, of a reverse operation type to the first power supply-side transistor, for controlling the connection of the first column wiring and a ground node, and a first polarity control line for causing the first power supply-side transistor or the first ground-side transistor to turn on and the other to turn off by a polar signal from a polar signal terminal, the first polarity control line being connected to the control terminals of the first power supply-side transistor and first ground-side transistor; a second unit including a second column wiring to

Abstract: A semiconductor integrated circuit (100) comprising: a plurality of processing circuits (11, 12, 13) each including a notification units for outputting a notification signal according to the processing state of the own processing circuit; a plurality of power supply switch units (SW1, SW2, SW3) for switching the connection states between the respective processing circuits and a power supply source; a power supply switch control circuit which is connected with the notification means (111, 121, 131), stores power supply control information (101) including a plurality of connection statuses, and controls the connection states on the basis of the notification signals and the power supply control information; and a data bus (BS) and the like connecting each of the processing circuits and the power supply switch control circuit, wherein: at least two or more of the plurality of processing circuits update the power supply control information via the data bus and the like before outputting a notification signal; and

Abstract: A semiconductor device includes a current control unit whose conductance is variable and a control unit configured to control the conductance of the current control unit. The current control unit is connected to a direct current power source in parallel with a load for the direct current power source, through a capacitor. The control unit sets the current control unit to a first conductance when the direct current power source and the load are not in a conduction state, and sets the current control unit to a second conductance larger than the first conductance when the direct current power source and the load are in the conduction state.

Abstract: An information processing apparatus according to the present invention includes: a detection unit that detects detection information that is information indicating an external state of the apparatus; a communication unit that receives reception information that is a determination result given by another apparatus; and a control unit that calculates a first determination result that is a result acquired by determining a state of a surrounding of the apparatus based on the detection information and the reception information, transmits the first determination result to the another apparatus via the communication unit, and activates a necessary function for the detection unit or the communication unit and stops an unnecessary function thereof.

Abstract: In order to stably write data into a magnetic memory that uses in-plane current-induced perpendicular switching of magnetization to write data, the magnetic memory includes a recording layer formed as a perpendicular magnetization film, an adjacent layer joined to an upper surface or a lower surface of the recording layer, an external magnetic field application part configured to apply a first external magnetic field to the recording layer in a first direction which is an in-plane direction of the recording layer, and a current application part configured to allow a write current to flow through the adjacent layer in the first direction or a second direction which is opposite to the first direction. The external magnetic field application part is configured to switch a direction of a second external magnetic field applied in a direction perpendicular to the first direction in accordance with a direction of the write current.

Abstract: In a programmable logic integrated circuit, providing a spare circuit in preparation for the occurrence of a defective element results in a redundant circuit configuration. A programmable logic integrated circuit according to the present invention has: a plurality of logic blocks; a switch block for switching the connections between row and column wires by nonvolatile switch elements for switching; and a shifter block for connecting an input/output wire to said switch block. The shifter block includes a redundant wire and is equipped with nonvolatile switch elements for shifting that control the connections of the wires constituting said redundant wire and said row wires.

Abstract: In a programmable logic integrated circuit, providing a spare circuit in preparation for the occurrence of a defective element results in a redundant circuit configuration. A programmable logic integrated circuit according to the present invention has: a plurality of logic blocks; a switch block for switching the connections between row and column wires by nonvolatile switch elements for switching; and a shifter block for connecting an input/output wire to said switch block. The shifter block includes a redundant wire and is equipped with nonvolatile switch elements for shifting that control the connections of the wires constituting said redundant wire and said row wires.

Abstract: A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network.