Abstract: A semiconductor memory device is provided with a memory array including memory cells arranged in rows and columns; and a sense amplifier circuit. Each of the memory cells includes at least one magnetoresistive element storing data, and an amplifying member used to amplify a signal generated by a current through the at least one magnetoresistive element. The sense amplifier circuit identifies data stored in the at least one magnetoresistive element in response to an output signal of the amplifying member.

Abstract: A toggle magnetic random access memory includes a first memory array, a second memory array and a controller. The first memory array includes a plurality of first memory cells including magnetoresistive elements. The second memory array includes a plurality of second memory cells including magnetoresistive elements and differs from the first memory array in write wirings used for writing. The controller controls the first memory array and the second memory array such that a first state in which a first burst write operation in the first memory array is executed and a second state in which a second burst write operation in the second memory array is executed are alternately executed in a continuous burst write mode. Accordingly, the continuous burst write operation can be executed at the high speed without any drop in the reliability and any increase in the circuit area.

Abstract: A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a reference cell each having a memory element that stores data based on change in resistance value. The read circuit includes: a voltage comparison unit that compares a value corresponding to a sense current from the selected cell with a value corresponding to a reference current from the reference cell; a first switch; and a second switch. Both of the first and second switches are provided at a subsequent stage of a decoder and at a preceding stage of the voltage comparison unit. The second switch circuit controls input of the value corresponding to the sense current to the voltage comparison unit, while the first switch circuit controls input of the value corresponding to the reference current to the voltage comparison unit.

Abstract: An MRAM has a plurality of bit lines, a reference bit line, a plurality of memory cells and reference cells and a read section. The memory cells are provided along the bit lines and the reference cells along the reference bit line. The memory cell and reference cell have a tunneling magnetic resistance and a reference tunneling magnetic resistance, each of which has a spontaneous magnetization whose direction is reversed in accordance with data stored therein. The read section has a first resistance section which contains a ninth terminal connected with a bit line and a tenth terminal connected with the first power supply, a second resistance section which contains an eleventh terminal connected with the reference bit line and a twelfth terminal connected with the first power supply, and a comparing section which compares a sense voltage on the ninth terminal and a reference voltage of the eleventh terminal.

Abstract: A MRAM includes: first wirings, second wirings, memory cells, a second sense amplifier and a first sense amplifier. The first wirings and second wirings are extended in a first and a second direction. The memory cells are placed correspondingly to positions where the first wirings are crossed with the second wirings. The second sense amplifier detects a state of a reference cell on the basis of an output from the reference cell provided by corresponding to a reference wiring. The first sense amplifier (2) detects a state of the memory cell on the basis of an output from the reference cell and an output from the memory cell. The memory cell includes a magnetic tunneling junction element having a laminated free layer. The magnetic tunneling junction element has a magnetization easy axis direction which is different from the first and second directions.

Abstract: A magnetization direction control method for controlling magnetization directions of first to third ferromagnetic layers (11-13) within a synthetic antiferromagnet structure (10A) having the first to the third ferromagnetic layers (11-13) and first and second non-magnetic layers (21, 22) interposed therebetween, without coupling antiferromagnetic material. The magnetization direction control method is composed of steps of (a) applying an external magnetic field HE to the synthetic antiferromagnet structure (10A) so as to direct the magnetizations of the first to third ferromagnetic layers in the same direction, and (b) reducing the external magnetic field to reverse the magnetization of one or some of the first to third ferromagnetic layers (11-13).

Abstract: A magneto-resistance element includes a free layer, a fixed layer and a non-magnetic layer interposed between the free layer and the fixed layer. The free layer has a first magnetic layer, a second magnetic layer, a third magnetic layer, a first non-magnetic layer interposed between the first magnetic layer and the second magnetic layer, and a second non-magnetic layer interposed between the second magnetic layer and the third magnetic layer. The first magnetic layer, the second magnetic layer and the third magnetic layer are coupled such that spontaneous magnetizations have a helical structure.

Abstract: A memory cell is used which includes a plurality of magneto-resistive elements and a plurality of laminated ferrimagnetic structure substances. The plurality of the magneto-resistive elements are placed corresponding to respective positions where a plurality of first wirings extended in a first direction intersects with a plurality of second wirings extended in a second direction which is substantially perpendicular to the first direction. The plurality of the laminated ferrimagnetic structure substances corresponds to the plurality of the magneto-resistive elements, respectively, is placed to have a distance of a predetermined range from the respective plurality of the magneto-resistive elements, and has a laminated ferrimagnetic structure. The magneto-resistive element includes a free layer having a laminated ferrimagnetic structure, a fixed layer, and a nonmagnetic layer interposed between the free layer and the fixed layer.

Abstract: A semiconductor memory device in which information is written into a storage element by flowing current. The semiconductor memory device has a shortened write speed and reduced power consumption by preventing parasitic capacitors from prolonging the time required for a write current to reach a predetermined value. The semiconductor memory device includes storage elements for storing information, a constant current source for writing information into the storage element by flowing current, and a boost circuit for charging parasitic capacitors by a time when an amount of a current flowed by the constant current source reaches an amount of a current required to write information into the storage element, at a predetermined position related to the storage element.

Abstract: By first readout, the current input from a selected cell is converted by a preamplifier and a VCO into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is counted by a counter 5 so as to be stored in a readout value register. A selected cell is then written to one of two storage states, and second readout is then carried out. The storage state of the selected cell is verified by comparing a count value of the counter for the second readout, a count value for the first readout as stored in a readout value register and a reference value stored in a reference value register to one another. By the use of the VCO, the integrating capacitor for the current or the generation of a reference pulse may be eliminated.

Abstract: There is provided a magnetization direction control method for controlling magnetization directions of first to third ferromagnetic layers (11-13) within a synthetic antiferromagnet structure (10A) having the first to the third ferromagnetic layers (11-13) and first and second non-magnetic layers (21, 22) interposed therebetween, without coupling antiferromagnetic material. The magnetization direction control method is composed of steps of (a) applying an external magnetic field HE to the synthetic antiferromagnet structure (10A) so as to direct the magnetizations of the first to third ferromagnetic layers in the same direction, and (b) reducing the external magnetic field to reverse the magnetization of one or some of the first to third ferromagnetic layers (11-13).

Abstract: A MRAM includes: first wirings, second wirings, memory cells, a second sense amplifier and a first sense amplifier. The first wirings and second wirings are extended in a first and a second direction. The memory cells are placed correspondingly to positions where the first wirings are crossed with the second wirings. The second sense amplifier detects a state of a reference cell on the basis of an output from the reference cell provided by corresponding to a reference wiring. The first sense amplifier (2) detects a state of the memory cell on the basis of an output from the reference cell and an output from the memory cell. The memory cell includes a magnetic tunneling junction element having a laminated free layer. The magnetic tunneling junction element has a magnetization easy axis direction which is different from the first and second directions.

Abstract: A semiconductor memory device is provided with a memory array including memory cells arranged in rows and columns; and a sense amplifier circuit. Each of the memory cells includes at least one magnetoresistive element storing data, and an amplifying member used to amplify a signal generated by a current through the at least one magnetoresistive element. The sense amplifier circuit identifies data stored in the at least one magnetoresistive element in response to an output signal of the amplifying member.

Abstract: In a magnetic random access memory, a memory cell includes a magnetic field generating section having an extension wiring line, and connected with a first selected bit line, a conductive pattern, and a magnetic resistance element having a spontaneous magnetization, storing a data and connected between the extension wiring line and the conductive pattern. In a data write operation into the memory cell, a write data is written in the magnetic resistance element of the memory cell by a write electric current which flows through the extension wiring line of the magnetic field generating section of the memory cell, and a value of the write data is determined based on a direction of the write electric current. In a data read operation from the memory cell, a read electric current flows through the extension wiring line of the magnetic field generating section and the magnetic resistance element in the memory cell.

Abstract: By a first readout, the current input from a selected cell is converted by a preamplifier and a voltage-controlled oscillator into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is counted by a counter to be stored in a readout value register. The selected cell is then written to one of two storage states, and a second readout is performed. The storage state of the selected cell is verified by comparing a count value of the counter for the second readout, a count value for the first readout as stored in the readout value register and a reference value stored in a reference value register.

Abstract: An MRAM has a plurality of bit lines, a reference bit line, a plurality of memory cells and reference cells and a read section. The memory cells are provided along the bit lines and the reference cells along the reference bit line. The memory cell and reference cell have a tunneling magnetic resistance and a reference tunneling magnetic resistance, each of which has a spontaneous magnetization whose direction is reversed in accordance with data stored therein. The read section has a first resistance section which contains a ninth terminal connected with a bit line and a tenth terminal connected with the first power supply, a second resistance section which contains an eleventh terminal connected with the reference bit line and a twelfth terminal connected with the first power supply, and a comparing section which compares a sense voltage on the ninth terminal and a reference voltage of the eleventh terminal.

Abstract: An improved magnetic random access memory (MRAM) has two sets of signal lines where each set is substantially perpendicular to the other, and memory cells located at the intersections of the signal lines. Each memory cell has a magneto-resistant element containing a magnetization layer whose magnetic characteristics change depending on the intensity of the magnetic field applied. A desired magnetic field can be applied to any cell by supplying appropriate write currents to the signal lines intersecting at that cell. The relationship between applied magnetic fields, two different threshold function values, and four different magnetic fields that result at each cell is disclosed. Better performance, namely, improved selectivity and a more stable write operation, results.

Abstract: By first readout, the current input from a selected cell 13 is converted by a preamplifier 3 and a VCO 4 into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is counted by a counter 5 so as to be stored in a readout value register 6. A selected cell is then written to one of two storage states, and second readout is then carried out. The storage state of the selected cell is verified by comparing a count value of the counter for the second readout, a count value for the first readout as stored in a readout value register and a reference value stored in a reference value register 7 to one another. By the use of the VCO, the integrating capacitor for the current or reference pulse generating means, so far needed, may be eliminated to assure a small area, low power consumption and fast readout.

Abstract: The present invention relates to a semiconductor memory device in which information is written into a storage element by flowing current. The invention aims at shortening write speed and reducing power consumption by preventing parasitic capacitors from prolonging the time required for a write current to reach a predetermined value. The apparatus includes storage elements for storing information, a constant current source for writing information into the storage element by flowing current, and a boost circuit for charging parasitic capacitors by a time when an amount of a current flowed by said constant current source reaches an amount of a current required to write information into the storage element, at a predetermined position related to the storage element.

Abstract: A magnetic random access memory is composed of a plurality of first signal lines provided to extend in a first direction, a plurality of second signal lines provided to extend in a second direction substantially perpendicular to the first direction, a plurality of memory cells respectively provided at the intersections of the plurality of first signal lines and the plurality of second signal lines, and a plurality of magnetic structures respectively provided to the plurality of memory cells. Each of the plurality of memory cells has a magneto-resistance element containing a spontaneous magnetization layer which has a first threshold function, and the direction of the spontaneous magnetization of the spontaneous magnetization layer is reversed when an element applied magnetic field having the intensity equal to or larger than a first threshold function value is applied.