Abstract: According to one embodiment, a method for manufacturing a semiconductor member is disclosed. The method can include measuring a first mass of a semiconductor substrate including a first semiconductor layer of a first conductivity type. The method can include forming a first opening in an upper surface of the first semiconductor layer. The method can include measuring a second mass of the semiconductor substrate in which the first opening is formed. In addition, the method can include when forming a second semiconductor layer of a second conductivity type in the first opening, changing an impurity concentration of the second conductivity type in the second semiconductor layer according to a difference in mass between the first mass and the second mass.

Abstract: According to one embodiment, a method for manufacturing a semiconductor member is disclosed. The method can include measuring a first mass of a semiconductor substrate including a first semiconductor layer of a first conductivity type. The method can include forming a first opening in an upper surface of the first semiconductor layer. The method can include measuring a second mass of the semiconductor substrate in which the first opening is formed. In addition, the method can include when forming a second semiconductor layer of a second conductivity type in the first opening, changing an impurity concentration of the second conductivity type in the second semiconductor layer according to a difference in mass between the first mass and the second mass.

Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a semiconductor layer having a first conductivity type on a semiconductor substrate, forming a trench in the semiconductor substrate and the semiconductor layer, forming a semiconductor film having a second conductivity type on an inner wall surface and a bottom surface of the trench, forming a first insulating film including silicon oxide on a side surface and a bottom surface of the semiconductor film, forming a second insulating film including silicon nitride on a side surface and a bottom surface of the first insulating film, and forming a third insulating film including silicon oxide on a side surface and a bottom surface of the second insulating film.

Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a semiconductor layer having a first conductivity type on a semiconductor substrate, forming a trench in the semiconductor substrate and the semiconductor layer, forming a semiconductor film having a second conductivity type on an inner wall surface and a bottom surface of the trench, forming a first insulating film including silicon oxide on a side surface and a bottom surface of the semiconductor film, forming a second insulating film including silicon nitride on a side surface and a bottom surface of the first insulating film, and forming a third insulating film including silicon oxide on a side surface and a bottom surface of the second insulating film.

Abstract: An information processing apparatus that processes a job, the apparatus comprises: a programmable circuit unit configured to configure a logic circuit; and a processing unit configured to process the job in accordance with a job processing request, wherein the processing unit selects, in accordance with a state of the programmable circuit unit, whether to process the job by using the programmable circuit unit being configuring a logic circuit corresponding to the job, or to process the job without using the programmable circuit unit.

Abstract: In some embodiments, according to one aspect, a semiconductor device includes a first semiconductor region of a first conductivity type that extends in a first direction, a second semiconductor region of a second conductivity type that is disposed adjacent to the first semiconductor region, extending in a second direction intersecting with the first direction, and having a surface which defines a first void in the second semiconductor region, a first insulating layer that is provided on the surface of the second semiconductor region which defines the first void, a third semiconductor region of the second conductivity type that is provided on the second semiconductor region and has a carrier concentration of the second conductivity type higher than a carrier concentration of the second conductivity type of the second semiconductor region, a fourth semiconductor region of the first conductivity type that is provided on the third semiconductor region, a gate insulating layer provided on the third semiconductor r

Abstract: According to one embodiment, a method for manufacturing a semiconductor device comprises making a first opening, ion-implanting an impurity of a second conductivity type, and forming a third semiconductor layer of the second conductivity type. The first opening is made in a second semiconductor layer. The second semiconductor layer is provided on a first semiconductor layer. The first opening extends in a second direction. A dimension in a third direction of an upper part of the first opening is longer than a dimension in the third direction of a lower part of the first opening. The third direction is perpendicular to the first direction and the second direction. The impurity of the second conductivity type is ion-implanted into a side surface of the lower part of the first opening. The third semiconductor layer of the second conductivity type is formed in an interior of the first opening.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device comprises making a first opening, ion-implanting an impurity of a second conductivity type, and forming a third semiconductor layer of the second conductivity type. The first opening is made in a second semiconductor layer. The second semiconductor layer is provided on a first semiconductor layer. The first opening extends in a second direction. A dimension in a third direction of an upper part of the first opening is longer than a dimension in the third direction of a lower part of the first opening. The third direction is perpendicular to the first direction and the second direction. The impurity of the second conductivity type is ion-implanted into a side surface of the lower part of the first opening. The third semiconductor layer of the second conductivity type is formed in an interior of the first opening.

Abstract: A semiconductor device includes first semiconductor regions of a first conductivity type spaced apart from each other and second semiconductor regions of a second conductivity type between adjacent first semiconductor regions. At least one second semiconductor region includes a void having at least one outer surface with a crystal plane orientation of (100). A third semiconductor region of the second conductivity type is on each second semiconductor region and a fourth semiconductor region of the first conductivity type is on the third semiconductor region. A gate electrode on is disposed on each first semiconductor region to be adjacent to a third semiconductor region via a gate insulation layer.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device comprises making a first opening, ion-implanting an impurity of a second conductivity type, and forming a third semiconductor layer of the second conductivity type. The first opening is made in a second semiconductor layer. The second semiconductor layer is provided on a first semiconductor layer. The first opening extends in a second direction. A dimension in a third direction of an upper part of the first opening is longer than a dimension in the third direction of a lower part of the first opening. The third direction is perpendicular to the first direction and the second direction. The impurity of the second conductivity type is ion-implanted into a side surface of the lower part of the first opening. The third semiconductor layer of the second conductivity type is formed in an interior of the first opening.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, a plurality of first regions that are spaced apart from each other along a first direction by portions of the semiconductor layer, each of the first regions including a first semiconductor region of a second conductivity type, a second region between the first regions in the first direction, the second region including a second semiconductor region of the first conductivity type and a first insulator between the second semiconductor region and the semiconductor layer, and a third region between the first region and the second region, the third region including a third semiconductor region of the first conductivity type and a second insulator.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a gate electrode, and a gate insulating layer. The first semiconductor region includes first portions and second portions. A length in a second direction of the second portion is longer than a length in the second direction of the first portion. The plurality of first portions and the plurality of second portions are provided alternately in a third direction. Part of the third semiconductor region is located between the second portions. An impurity concentration of the second conductivity type of the third semiconductor region is lower than an impurity concentration of the second conductivity type of the second semiconductor region.

Abstract: A semiconductor device includes first semiconductor regions of a first conductivity type spaced apart from each other and second semiconductor regions of a second conductivity type between adjacent first semiconductor regions. At least one second semiconductor region includes a void having at least one outer surface with a crystal plane orientation of (100). A third semiconductor region of the second conductivity type is on each second semiconductor region and a fourth semiconductor region of the first conductivity type is on the third semiconductor region. A gate electrode on is disposed on each first semiconductor region to be adjacent to a third semiconductor region via a gate insulation layer.

Abstract: An information processing apparatus that processes a job, the apparatus comprises: a programmable circuit unit configured to configure a logic circuit; and a processing unit configured to process the job in accordance with a job processing request, wherein the processing unit selects, in accordance with a state of the programmable circuit unit, whether to process the job by using the programmable circuit unit being configuring a logic circuit corresponding to the job, or to process the job without using the programmable circuit unit.

Abstract: A semiconductor manufacturing apparatus includes a chamber configured to house a semiconductor substrate therein. A vacuum part depressurizes inside of the chamber. A heater heats the semiconductor substrate. The vacuum part depressurizes the inside of the chamber in order to freeze water attached to the semiconductor substrate. The heater heats the semiconductor substrate in order to sublimate water frozen on the semiconductor substrate.

Abstract: An information processing apparatus includes: a storage unit storing a maximum acceptable number of sheets of recording paper that can be processed by a post processing apparatus; a post process setting unit setting a predetermined post process to be performed by using the post processing apparatus; a generating unit generating bitmap data in units of physical pages based on logical page data; a transmitting unit transmitting the generated bitmap data to an image forming apparatus; a determining unit determining whether the post process can be performed based on the number of physical pages generated from the logical page data and the maximum acceptable number if setting has been done so as to perform the predetermined post process on the logical page data; and a control unit controlling a bitmap data generating process performed by the generating unit and a bitmap data transmitting process performed by the transmitting unit based on the determination made by the determining unit.

Abstract: In a line by line image forming apparatus, line switching information which depends on scan line curve and an overlap data length to be read that overlaps across a plurality of lines before and after a switching position instructed by line switching information are set in a register. If switching to the line above or below is instructed by the line switching information, an address generating unit, when reading image data from an image memory, generates the read address and read data length of the image memory in accordance with the line switching information and the overlap data length, and reads image data corresponding to a current line and the line above or below the current line in accordance with the generated data.

Abstract: In order to realize both the security and convenience upon using the image forming apparatus, whether or not to store an operation history is selected for each operation mode. A desired one of a plurality of operation modes is designated. When the designated operation mode is selected to store the operation mode, the operation history is stored in accordance with the operation of the operation mode.

Abstract: In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

Abstract: In a line by line image forming apparatus, line switching information which depends on scan line curve and an overlap data length to be read that overlaps across a plurality of lines before and after a switching position instructed by line switching information are set in a register. If switching to the line above or below is instructed by the line switching information, an address generating unit, when reading image data from an image memory, generates the read address and read data length of the image memory in accordance with the line switching information and the overlap data length, and reads image data corresponding to a current line and the line above or below the current line in accordance with the generated data.