Abstract: A lithium secondary battery includes a positive electrode, a negative electrode, an electrolyte, and a separator. The electrolyte contains a lithium salt of an anion represented by Formula (1) and a lithium cation and an organic salt of an anion represented by Formula (1) and a cation represented by Formula (2).

Abstract: A method for producing a negative electrode, including a step of subjecting a copper foil to a plasma treatment, a step of coating the copper foil subjected to the plasma treatment, with a slurry including an active material containing a silicon atom, and a step of subjecting the copper foil coated with the slurry to a heat treatment to form an intermetallic compound of copper and silicon at an interface between the copper foil and the active material. A negative electrode including a copper foil, an active material layer including an active material containing a silicon atom on the copper foil, and copper silicide at an interface between the copper foil and the active material.

Abstract: There is provided a lithium ion secondary battery having a high capacity retention rate in the charge-discharge cycles. There is provided a positive electrode for a lithium ion secondary battery, including a positive electrode active material including a compound represented by the following formula (1), Lix(NiyCozAlw)O2, wherein, in formula (1), 0.95?x?1.05, 0.70?y?0.85, 0.05?z?0.20, 0.00?w?0.10, and y+z+w=1, and a compound represented by the following formula (2), Li1+uMn2?u/3O4, wherein, in formula (2), wherein the content of the alkali metal hydroxide in the positive electrode active material is 0.15% by mass or less.

Abstract: A method for producing a negative electrode, including a step of subjecting a copper foil to a plasma treatment, a step of coating the copper foil subjected to the plasma treatment, with a slurry including an active material containing a silicon atom, and a step of subjecting the copper foil coated with the slurry to a heat treatment to form an intermetallic compound of copper and silicon at an interface between the copper foil and the active material. A negative electrode including a copper foil, an active material layer including an active material containing a silicon atom on the copper foil, and copper silicide at an interface between the copper foil and the active material.

Abstract: Improved control over formation of low k air gaps in interlayer insulating films is achieved by plasma pretreatment of the region of the insulating film to be removed. The intended air gap region is exposed through a mask while the film region to be preserved is shielded by the mask. The intended air gap region is then exposed to a plasma so as to render it more susceptible to removal in a subsequent treatment. One or more Cu interconnects are embedded in both regions of the insulator film. The insulator film in the intended air gap region is then selectively removed to form air gaps adjacent a Cu interconnect in that region.

Abstract: A designing method for a semiconductor device includes: determining a placement of metal wirings to be connected to contact holes and a placement of through-holes for preparing the contact holes. The determining step includes: specifying areas in one of the metal wirings to be exposed by the through-holes, specifying a capacitance of the metal wirings, and determining the placement of the metal wirings such that damage to the areas is suppressed in a case where electric charges accumulated in the capacitance are transferred from one of the metal wirings to a polar solvent through the areas.

Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).

Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film and a second interlayer insulating film formed of a low dielectric constant film on a substrate, forming via holes by using a first resist pattern formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern on the second interlayer insulating film. After the wet treatment before a second antireflection coating is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern.

Abstract: Precision in an etching process is to be improved. A detecting unit 404 detects a variation of plasma emission intensity at a plurality of wavelengths (an emission band having an intensity peak in the proximity of 358 nm and an emission band having an intensity peak in the proximity of 387 nm) during a dry etching process being performed on either of a nitrogen-containing film formed on a semiconductor substrate or a non-nitrogen film provided in direct contact with the nitrogen-containing film in an etching apparatus 402. An arithmetic processing unit 406 performs calculation based on detected variation. A control unit 410 determines an endpoint of the dry etching process in consideration of the calculation result.

Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).

Abstract: Precision in an etching process is to be improved. A detecting unit 404 detects a variation of plasma emission intensity at a plurality of wavelengths (an emission band having an intensity peak in the proximity of 358 nm and an emission band having an intensity peak in the proximity of 387 nm) during a dry etching process being performed on either of a nitrogen-containing film formed on a semiconductor substrate or a non-nitrogen film provided in direct contact with the nitrogen-containing film in an etching apparatus 402. An arithmetic processing unit 406 performs calculation based on detected variation. A control unit 410 determines an endpoint of the dry etching process in consideration of the calculation result.

Abstract: A photo mask for fabricating a semiconductor device having a dual damascene structure which has a via coupled with a lower wiring layer and has an upper wiring layer coupled with the via. The via and the upper wiring layer are fabricated by filling a via hole and a wiring groove formed in an interlayer insulating film that is formed on the lower wiring layer with a wiring material. The photo mask has a via alignment mark which is used for aligning the via hole with respect to the lower wiring layer and/or a via alignment mark which is used for aligning the wiring groove with respect to the via hole. The width of the via alignment mark is equal to or larger than the width which is optically detectable and an aspect ratio of the via alignment mark is equal to or larger than one fourth of the aspect ratio of the via hole. Preferably, the width of the via alignment mark is equal to or larger than the width of the via hole.

Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).

Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of forming the metal-silicide layer on the surface of the impurity-diffused region between the steps of implanting impurities to form an impurity-implanted region and annealing for reactions of cobalt and silicon of the diffused layer. The above-mentioned method of forming the metal-silicide layer on the surface of the impurity-diffused region proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of implanting impurities to form an impurity-implanted region and annealing for refractory-metal-silicification of the diffused layer. The refractory-metal-silicification of the diffused regions proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of implanting impurities to form an impurity-implanted region and annealing for refractory-metal-silicification of the diffused layer. The refractory-metal-silicification of the diffused regions proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Abstract: Cobalt is sputtered on a silicon wafer in a deposition chamber of a magnetron sputtering system, and is conveyed to a load-lock chamber where a partial pressure of oxygen and/or the water concentration is controlled with introduction of nitrogen so as to present dicobalt disilicide layers from oxidation, thereby improving the production yield and reliability of the silicide layer morphology.

Abstract: In a method of fabricating a semiconductor device in which a metal film is formed that is to serve as the diffusion barrier layer material of a plug electrode material that is used when forming a plug electrode on a diffusion layer electrode or a gate electrode in which a metal silicide layer has been formed, increase in the resistance of the plug electrode is prevented. Immediately after the formation of a plug hole by a dry etching method, silicon ions are implanted with an acceleration voltage of at least 20 KeV and at a dosage of at least 1×1013 atoms/cm2, following which a titanium film and a titanium nitride film are formed as the metal film by a sputtering method without carrying out etching by an RF etching method.

Abstract: In a method of fabricating a semiconductor device in which a metal film is formed that is to serve as the diffusion barrier layer material of a plug electrode material that is used when forming a plug electrode on a diffusion layer electrode or a gate electrode in which a metal silicide layer has been formed, increase in the resistance of the plug electrode is prevented. Immediately after the formation of a plug hole by a dry etching method, silicon ions are implanted with an acceleration voltage of at least 20 KeV and at a dosage of at least 1×1013 atoms/cm2 following which a titanium film and a titanium nitride film are formed as the metal film by a sputtering method without carrying out etching by an RF etching method.

Abstract: A photo mask for fabricating a semiconductor device having a dual damascene structure which has a via coupled with a lower wiring layer and has an upper wiring layer coupled with the via. The via and the upper wiring layer are fabricated by filling a via hole and a wiring groove formed in an interlayer insulating film that is formed on the lower wiring layer with a wiring material. The photo mask has a via alignment mark which is used for aligning the via hole with respect to the lower wiring layer and/or a via alignment mark which is used for aligning the wiring groove with respect to the via hole. The width of the via alignment mark is equal to or larger than the width which is optically detectable and an aspect ratio of the via alignment mark is equal to or larger than one fourth of the aspect ratio of the via hole. Preferably, the width of the via alignment mark is equal to or larger than the width of the via hole.