Patents by Inventor Nobuaki Kakinuma
Nobuaki Kakinuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11425365Abstract: A photoelectric conversion device comprising: a first substrate that includes a pixel circuit including a photoelectric conversion element; a second substrate having a signal processing circuit that drives the pixel circuit or processes a signal from the pixel circuit; a connection part electrically connecting the first substrate and the second substrate; and an inspection circuit, wherein the inspection circuit is formed in one of the first and second substrates and is connected to a wire supplying a first potential and being provided in the one of the first and second substrates, and the inspection circuit is connected via the connection part to a wire supplying a second potential and being provided in the other of the first and second substrates.Type: GrantFiled: December 4, 2019Date of Patent: August 23, 2022Assignee: Canon Kabushiki KaishaInventors: Ryunosuke Ishii, Akira Oseto, Tatsunori Kato, Takanori Watanabe, Nobuaki Kakinuma, Hiroaki Kobayashi, Katsuhito Sakurai
-
Publication number: 20210358904Abstract: A photoelectric conversion apparatus includes a pad, a first protection circuit provided on a first semiconductor substrate, and a second protection circuit provided on a second semiconductor substrate. The first semiconductor substrate, which includes a plurality of photoelectric conversion units each receiving incident light and generating signal charge, and the second semiconductor substrate, which includes at least one signal processing circuit that processes an input signal based on the generated signal charge, are laminated. The pad receives a power supply voltage as input from an outside of the photoelectric conversion apparatus. At least one of the first protection circuit or the second protection circuit is provided on an outside of a region in which the pad is provided, in planar view. At least one of the first protection circuit or the second protection circuit is connected to the pad.Type: ApplicationFiled: May 11, 2021Publication date: November 18, 2021Inventors: Akira Oseto, Nobuaki Kakinuma, Tatsunori Kato, Ryunosuke Ishii, Koji Hara
-
Patent number: 10937822Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.Type: GrantFiled: February 26, 2019Date of Patent: March 2, 2021Assignee: Canon Kabushiki KaishaInventors: Mineo Shimotsusa, Masatsugu Itahashi, Yusuke Onuki, Nobuaki Kakinuma, Masato Fujita
-
Publication number: 20200195916Abstract: A photoelectric conversion device comprising: a first substrate that includes a pixel circuit including a photoelectric conversion element; a second substrate having a signal processing circuit that drives the pixel circuit or processes a signal from the pixel circuit; a connection part electrically connecting the first substrate and the second substrate; and an inspection circuit, wherein the inspection circuit is formed in one of the first and second substrates and is connected to a wire supplying a first potential and being provided in the one of the first and second substrates, and the inspection circuit is connected via the connection part to a wire supplying a second potential and being provided in the other of the first and second substrates.Type: ApplicationFiled: December 4, 2019Publication date: June 18, 2020Inventors: Ryunosuke Ishii, Akira Oseto, Tatsunori Kato, Takanori Watanabe, Nobuaki Kakinuma, Hiroaki Kobayashi, Katsuhito Sakurai
-
Patent number: 10658421Abstract: A method of manufacturing a photoelectric conversion apparatus includes heating a semiconductor substrate while a pixel circuit area is covered with an insulator film, performing ion implantation into the pixel circuit area through the insulator film, performing ion implantation into a peripheral circuit area after the heating, and forming a side wall on a side surface of a gate electrode of a transistor after the performing ion implantation into the peripheral circuit area.Type: GrantFiled: August 28, 2018Date of Patent: May 19, 2020Assignee: CANON KABUSHIKI KAISHAInventors: Takehito Okabe, Mitsuhiro Yomori, Nobuaki Kakinuma, Toshihiro Shoyama, Masashi Kusukawa
-
Patent number: 10475829Abstract: A semiconductor apparatus includes a conductive member including a polycrystalline silicon layer having a first, second and third portions, an interlayer insulation film that covers the conductive member, a first silicon nitride layer arranged between the interlayer insulation film and the third portion, a second silicon nitride layer arranged between the interlayer insulation film and the first portion and between the interlayer insulation layer and the second portion, a first contact plug disposed above the first portion and penetrating the interlayer insulation film and the second silicon nitride layer to connect to the conductive member, and a second contact plug disposed above the second portion and penetrating the interlayer insulation film and the second silicon nitride layer to connect to the conductive member. The first silicon nitride layer is disposed between the first and second contact plugs, and apart from the first and second contact plugs.Type: GrantFiled: July 3, 2018Date of Patent: November 12, 2019Assignee: CANON KABUSHIKI KAISHAInventors: Mitsuhiro Yomori, Takehito Okabe, Nobuaki Kakinuma, Takashi Okagawa
-
Publication number: 20190198537Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.Type: ApplicationFiled: February 26, 2019Publication date: June 27, 2019Inventors: Mineo Shimotsusa, Masatsugu Itahashi, Yusuke Onuki, Nobuaki Kakinuma, Masato Fujita
-
Patent number: 10332783Abstract: A method of manufacturing a semiconductor device is provided. The method comprises arranging an insulator, forming a hole in the insulator, first exposing for exposing a first portion of a photoresist arranged on the insulator, second exposing for exposing a second portion of the photoresist, after the first and second exposing, forming a trench in the insulator in accordance with etching the insulator using a resist pattern formed by developing the photoresist as a mask and embedding a conductor in the hole and the trench. The trench includes a first trench corresponding to the exposure of the first portion of the resist pattern and a second trench corresponding to the exposure of the second portion of the resist pattern. The first and second trench each communicate with the hole and the hole is deeper than the first and second trench.Type: GrantFiled: April 4, 2018Date of Patent: June 25, 2019Assignee: CANON KABUSHIKI KAISHAInventor: Nobuaki Kakinuma
-
Patent number: 10263029Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.Type: GrantFiled: November 30, 2017Date of Patent: April 16, 2019Assignee: Canon Kabushiki KaishaInventors: Mineo Shimotsusa, Masatsugu Itahashi, Yusuke Onuki, Nobuaki Kakinuma, Masato Fujita
-
Publication number: 20190067364Abstract: A method of manufacturing a photoelectric conversion apparatus includes heating a semiconductor substrate while a pixel circuit area is covered with an insulator film, performing ion implantation into the pixel circuit area through the insulator film, performing ion implantation into a peripheral circuit area after the heating, and forming a side wall on a side surface of a gate electrode of a transistor after the performing ion implantation into the peripheral circuit area.Type: ApplicationFiled: August 28, 2018Publication date: February 28, 2019Inventors: Takehito Okabe, Mitsuhiro Yomori, Nobuaki Kakinuma, Toshihiro Shoyama, Masashi Kusukawa
-
Publication number: 20190019825Abstract: A semiconductor apparatus includes a conductive member including a polycrystalline silicon layer having a first, second and third portions, an interlayer insulation film that covers the conductive member, a first silicon nitride layer arranged between the interlayer insulation film and the third portion, a second silicon nitride layer arranged between the interlayer insulation film and the first portion and between the interlayer insulation layer and the second portion, a first contact plug disposed above the first portion and penetrating the interlayer insulation film and the second silicon nitride layer to connect to the conductive member, and a second contact plug disposed above the second portion and penetrating the interlayer insulation film and the second silicon nitride layer to connect to the conductive member. The first silicon nitride layer is disposed between the first and second contact plugs, and apart from the first and second contact plugs.Type: ApplicationFiled: July 3, 2018Publication date: January 17, 2019Inventors: Mitsuhiro Yomori, Takehito Okabe, Nobuaki Kakinuma, Takashi Okagawa
-
Publication number: 20180308747Abstract: A method of manufacturing a semiconductor device is provided. The method comprises arranging an insulator, forming a hole in the insulator, first exposing for exposing a first portion of a photoresist arranged on the insulator, second exposing for exposing a second portion of the photoresist, after the first and second exposing, forming a trench in the insulator in accordance with etching the insulator using a resist pattern formed by developing the photoresist as a mask and embedding a conductor in the hole and the trench. The trench includes a first trench corresponding to the exposure of the first portion of the resist pattern and a second trench corresponding to the exposure of the second portion of the resist pattern. The first and second trench each communicate with the hole and the hole is deeper than the first and second trench.Type: ApplicationFiled: April 4, 2018Publication date: October 25, 2018Inventor: Nobuaki Kakinuma
-
Patent number: 10026774Abstract: A method of manufacturing a solid-state image sensor including preparing a wafer including a pixel region where a photoelectric conversion element is provided, a peripheral circuit region where a gate electrode of a peripheral MOS transistor for constituting a peripheral circuit is provided, and a scribe region. The method includes forming an insulating film covering the pixel region, the peripheral circuit region, and the scribe region, and forming a sidewall spacer on a side surface of the gate electrode by etching the insulating film so that portions of the insulating film remains to cover the pixel region and the scribe region, and forming a metal silicide layer in the peripheral circuit region by using, as a mask for protection from silicidation, the insulating film covering the pixel region and the scribe region.Type: GrantFiled: May 27, 2015Date of Patent: July 17, 2018Assignee: CANON KABUSHIKI KAISHAInventors: Yusuke Onuki, Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Takumi Ogino, Keita Torii
-
Publication number: 20180090527Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.Type: ApplicationFiled: November 30, 2017Publication date: March 29, 2018Inventors: Mineo Shimotsusa, Masatsugu Itahashi, Yusuke Onuki, Nobuaki Kakinuma, Masato Fujita
-
Patent number: 9865637Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.Type: GrantFiled: October 28, 2015Date of Patent: January 9, 2018Assignee: Canon Kabushiki KaishaInventors: Mineo Shimotsusa, Masatsugu Itahashi, Yusuke Onuki, Nobuaki Kakinuma, Masato Fujita
-
Patent number: 9716126Abstract: A method of manufacturing a solid-state image sensor includes forming a first element isolation and a first active region of a pixel area, and a second isolation and a second active region of a peripheral circuit area, forming a gate electrode film covering the first element isolation, the first active region, the second element isolation and the second active region, implanting an n-type impurity selectively into at least a part of the gate electrode film corresponding to the pixel area, and forming, after the implanting of the n-type impurity, a first gate electrode of the pixel area and a second gate electrode of the peripheral circuit area by patterning the gate electrode film. The part of the gate electrode film includes a portion located above a boundary between the first element isolation and the first active region.Type: GrantFiled: June 1, 2015Date of Patent: July 25, 2017Assignee: CANON KABUSHIKI KAISHAInventors: Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Yusuke Onuki, Takumi Ogino, Keita Torii
-
Patent number: 9608033Abstract: A solid-state image sensor includes a pixel area and a peripheral circuit area. The pixel area includes a first MOS, and the peripheral circuit area includes a second MOS. A method includes forming a gate of the first MOS and a gate of the second MOS, forming a first insulating film to cover the gates of the first and second MOSs, etching the first insulating film in the peripheral circuit area in a state that the pixel area is masked to form a side spacer on a side face of the gate of the second MOS, etching the first insulating film in the pixel area in a state that the peripheral circuit area is masked, and forming the second insulating film to cover the gates of the first and second MOSs and the side spacers.Type: GrantFiled: April 21, 2015Date of Patent: March 28, 2017Assignee: CANON KABUSHIKI KAISHAInventors: Masatsugu Itahashi, Seiichi Tamura, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Yusuke Onuki
-
Publication number: 20160126278Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.Type: ApplicationFiled: October 28, 2015Publication date: May 5, 2016Inventors: Mineo Shimotsusa, Masatsugu Itahashi, Yusuke Onuki, Nobuaki Kakinuma, Masato Fujita
-
Publication number: 20150364517Abstract: A method of manufacturing a solid-state image sensor including preparing a wafer including a pixel region where a photoelectric conversion element is provided, a peripheral circuit region where a gate electrode of a peripheral MOS transistor for constituting a peripheral circuit is provided, and a scribe region. The method includes forming an insulating film covering the pixel region, the peripheral circuit region, and the scribe region, and forming a sidewall spacer on a side surface of the gate electrode by etching the insulating film so that portions of the insulating film remains to cover the pixel region and the scribe region, and forming a metal silicide layer in the peripheral circuit region by using, as a mask for protection from silicidation, the insulating film covering the pixel region and the scribe region.Type: ApplicationFiled: May 27, 2015Publication date: December 17, 2015Inventors: Yusuke Onuki, Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Takumi Ogino, Keita Torii
-
Publication number: 20150364522Abstract: A method of manufacturing a solid-state image sensor includes forming a first element isolation and a first active region of a pixel area, and a second isolation and a second active region of a peripheral circuit area, forming a gate electrode film covering the first element isolation, the first active region, the second element isolation and the second active region, implanting an n-type impurity selectively into at least a part of the gate electrode film corresponding to the pixel area, and forming, after the implanting of the n-type impurity, a first gate electrode of the pixel area and a second gate electrode of the peripheral circuit area by patterning the gate electrode film. The part of the gate electrode film includes a portion located above a boundary between the first element isolation and the first active region.Type: ApplicationFiled: June 1, 2015Publication date: December 17, 2015Inventors: Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Yusuke Onuki, Takumi Ogino, Keita Torii