Patents by Inventor Nobuaki Kakinuma

Nobuaki Kakinuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200195916
    Abstract: A photoelectric conversion device comprising: a first substrate that includes a pixel circuit including a photoelectric conversion element; a second substrate having a signal processing circuit that drives the pixel circuit or processes a signal from the pixel circuit; a connection part electrically connecting the first substrate and the second substrate; and an inspection circuit, wherein the inspection circuit is formed in one of the first and second substrates and is connected to a wire supplying a first potential and being provided in the one of the first and second substrates, and the inspection circuit is connected via the connection part to a wire supplying a second potential and being provided in the other of the first and second substrates.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 18, 2020
    Inventors: Ryunosuke Ishii, Akira Oseto, Tatsunori Kato, Takanori Watanabe, Nobuaki Kakinuma, Hiroaki Kobayashi, Katsuhito Sakurai
  • Patent number: 10658421
    Abstract: A method of manufacturing a photoelectric conversion apparatus includes heating a semiconductor substrate while a pixel circuit area is covered with an insulator film, performing ion implantation into the pixel circuit area through the insulator film, performing ion implantation into a peripheral circuit area after the heating, and forming a side wall on a side surface of a gate electrode of a transistor after the performing ion implantation into the peripheral circuit area.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 19, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takehito Okabe, Mitsuhiro Yomori, Nobuaki Kakinuma, Toshihiro Shoyama, Masashi Kusukawa
  • Patent number: 10475829
    Abstract: A semiconductor apparatus includes a conductive member including a polycrystalline silicon layer having a first, second and third portions, an interlayer insulation film that covers the conductive member, a first silicon nitride layer arranged between the interlayer insulation film and the third portion, a second silicon nitride layer arranged between the interlayer insulation film and the first portion and between the interlayer insulation layer and the second portion, a first contact plug disposed above the first portion and penetrating the interlayer insulation film and the second silicon nitride layer to connect to the conductive member, and a second contact plug disposed above the second portion and penetrating the interlayer insulation film and the second silicon nitride layer to connect to the conductive member. The first silicon nitride layer is disposed between the first and second contact plugs, and apart from the first and second contact plugs.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 12, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Mitsuhiro Yomori, Takehito Okabe, Nobuaki Kakinuma, Takashi Okagawa
  • Publication number: 20190198537
    Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 27, 2019
    Inventors: Mineo Shimotsusa, Masatsugu Itahashi, Yusuke Onuki, Nobuaki Kakinuma, Masato Fujita
  • Patent number: 10332783
    Abstract: A method of manufacturing a semiconductor device is provided. The method comprises arranging an insulator, forming a hole in the insulator, first exposing for exposing a first portion of a photoresist arranged on the insulator, second exposing for exposing a second portion of the photoresist, after the first and second exposing, forming a trench in the insulator in accordance with etching the insulator using a resist pattern formed by developing the photoresist as a mask and embedding a conductor in the hole and the trench. The trench includes a first trench corresponding to the exposure of the first portion of the resist pattern and a second trench corresponding to the exposure of the second portion of the resist pattern. The first and second trench each communicate with the hole and the hole is deeper than the first and second trench.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: June 25, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Nobuaki Kakinuma
  • Patent number: 10263029
    Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 16, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mineo Shimotsusa, Masatsugu Itahashi, Yusuke Onuki, Nobuaki Kakinuma, Masato Fujita
  • Publication number: 20190067364
    Abstract: A method of manufacturing a photoelectric conversion apparatus includes heating a semiconductor substrate while a pixel circuit area is covered with an insulator film, performing ion implantation into the pixel circuit area through the insulator film, performing ion implantation into a peripheral circuit area after the heating, and forming a side wall on a side surface of a gate electrode of a transistor after the performing ion implantation into the peripheral circuit area.
    Type: Application
    Filed: August 28, 2018
    Publication date: February 28, 2019
    Inventors: Takehito Okabe, Mitsuhiro Yomori, Nobuaki Kakinuma, Toshihiro Shoyama, Masashi Kusukawa
  • Publication number: 20190019825
    Abstract: A semiconductor apparatus includes a conductive member including a polycrystalline silicon layer having a first, second and third portions, an interlayer insulation film that covers the conductive member, a first silicon nitride layer arranged between the interlayer insulation film and the third portion, a second silicon nitride layer arranged between the interlayer insulation film and the first portion and between the interlayer insulation layer and the second portion, a first contact plug disposed above the first portion and penetrating the interlayer insulation film and the second silicon nitride layer to connect to the conductive member, and a second contact plug disposed above the second portion and penetrating the interlayer insulation film and the second silicon nitride layer to connect to the conductive member. The first silicon nitride layer is disposed between the first and second contact plugs, and apart from the first and second contact plugs.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 17, 2019
    Inventors: Mitsuhiro Yomori, Takehito Okabe, Nobuaki Kakinuma, Takashi Okagawa
  • Publication number: 20180308747
    Abstract: A method of manufacturing a semiconductor device is provided. The method comprises arranging an insulator, forming a hole in the insulator, first exposing for exposing a first portion of a photoresist arranged on the insulator, second exposing for exposing a second portion of the photoresist, after the first and second exposing, forming a trench in the insulator in accordance with etching the insulator using a resist pattern formed by developing the photoresist as a mask and embedding a conductor in the hole and the trench. The trench includes a first trench corresponding to the exposure of the first portion of the resist pattern and a second trench corresponding to the exposure of the second portion of the resist pattern. The first and second trench each communicate with the hole and the hole is deeper than the first and second trench.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 25, 2018
    Inventor: Nobuaki Kakinuma
  • Patent number: 10026774
    Abstract: A method of manufacturing a solid-state image sensor including preparing a wafer including a pixel region where a photoelectric conversion element is provided, a peripheral circuit region where a gate electrode of a peripheral MOS transistor for constituting a peripheral circuit is provided, and a scribe region. The method includes forming an insulating film covering the pixel region, the peripheral circuit region, and the scribe region, and forming a sidewall spacer on a side surface of the gate electrode by etching the insulating film so that portions of the insulating film remains to cover the pixel region and the scribe region, and forming a metal silicide layer in the peripheral circuit region by using, as a mask for protection from silicidation, the insulating film covering the pixel region and the scribe region.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: July 17, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yusuke Onuki, Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Takumi Ogino, Keita Torii
  • Publication number: 20180090527
    Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 29, 2018
    Inventors: Mineo Shimotsusa, Masatsugu Itahashi, Yusuke Onuki, Nobuaki Kakinuma, Masato Fujita
  • Patent number: 9865637
    Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: January 9, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mineo Shimotsusa, Masatsugu Itahashi, Yusuke Onuki, Nobuaki Kakinuma, Masato Fujita
  • Patent number: 9716126
    Abstract: A method of manufacturing a solid-state image sensor includes forming a first element isolation and a first active region of a pixel area, and a second isolation and a second active region of a peripheral circuit area, forming a gate electrode film covering the first element isolation, the first active region, the second element isolation and the second active region, implanting an n-type impurity selectively into at least a part of the gate electrode film corresponding to the pixel area, and forming, after the implanting of the n-type impurity, a first gate electrode of the pixel area and a second gate electrode of the peripheral circuit area by patterning the gate electrode film. The part of the gate electrode film includes a portion located above a boundary between the first element isolation and the first active region.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: July 25, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Yusuke Onuki, Takumi Ogino, Keita Torii
  • Patent number: 9608033
    Abstract: A solid-state image sensor includes a pixel area and a peripheral circuit area. The pixel area includes a first MOS, and the peripheral circuit area includes a second MOS. A method includes forming a gate of the first MOS and a gate of the second MOS, forming a first insulating film to cover the gates of the first and second MOSs, etching the first insulating film in the peripheral circuit area in a state that the pixel area is masked to form a side spacer on a side face of the gate of the second MOS, etching the first insulating film in the pixel area in a state that the peripheral circuit area is masked, and forming the second insulating film to cover the gates of the first and second MOSs and the side spacers.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: March 28, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masatsugu Itahashi, Seiichi Tamura, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Yusuke Onuki
  • Publication number: 20160126278
    Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 5, 2016
    Inventors: Mineo Shimotsusa, Masatsugu Itahashi, Yusuke Onuki, Nobuaki Kakinuma, Masato Fujita
  • Publication number: 20150364517
    Abstract: A method of manufacturing a solid-state image sensor including preparing a wafer including a pixel region where a photoelectric conversion element is provided, a peripheral circuit region where a gate electrode of a peripheral MOS transistor for constituting a peripheral circuit is provided, and a scribe region. The method includes forming an insulating film covering the pixel region, the peripheral circuit region, and the scribe region, and forming a sidewall spacer on a side surface of the gate electrode by etching the insulating film so that portions of the insulating film remains to cover the pixel region and the scribe region, and forming a metal silicide layer in the peripheral circuit region by using, as a mask for protection from silicidation, the insulating film covering the pixel region and the scribe region.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 17, 2015
    Inventors: Yusuke Onuki, Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Takumi Ogino, Keita Torii
  • Publication number: 20150364522
    Abstract: A method of manufacturing a solid-state image sensor includes forming a first element isolation and a first active region of a pixel area, and a second isolation and a second active region of a peripheral circuit area, forming a gate electrode film covering the first element isolation, the first active region, the second element isolation and the second active region, implanting an n-type impurity selectively into at least a part of the gate electrode film corresponding to the pixel area, and forming, after the implanting of the n-type impurity, a first gate electrode of the pixel area and a second gate electrode of the peripheral circuit area by patterning the gate electrode film. The part of the gate electrode film includes a portion located above a boundary between the first element isolation and the first active region.
    Type: Application
    Filed: June 1, 2015
    Publication date: December 17, 2015
    Inventors: Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Yusuke Onuki, Takumi Ogino, Keita Torii
  • Publication number: 20150325620
    Abstract: A solid-state image sensor includes a pixel area and a peripheral circuit area. The pixel area includes a first MOS, and the peripheral circuit area includes a second MOS. A method includes forming a gate of the first MOS and a gate of the second MOS, forming a first insulating film to cover the gates of the first and second MOSs, etching the first insulating film in the peripheral circuit area in a state that the pixel area is masked to form a side spacer on a side face of the gate of the second MOS, etching the first insulating film in the pixel area in a state that the peripheral circuit area is masked, and forming the second insulating film to cover the gates of the first and second MOSs and the side spacers.
    Type: Application
    Filed: April 21, 2015
    Publication date: November 12, 2015
    Inventors: Masatsugu Itahashi, Seiichi Tamura, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Yusuke Onuki
  • Patent number: 8729539
    Abstract: Provided is a light-emitting apparatus which, without using an insulating film for separating pixels, inhibits leakage current between adjacent pixels and which accommodates higher resolution. By providing a groove in an insulating layer along an edge of a first electrode, the thickness of a first charge transport layer is reduced to inhibit leakage current between adjacent pixels.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: May 20, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuaki Kakinuma, Seishi Miura, Koichi Ishige, Nobuhiko Sato
  • Publication number: 20130234120
    Abstract: Provided is a light-emitting apparatus which, without using an insulating film for separating pixels, inhibits leakage current between adjacent pixels and which accommodates higher resolution. By providing a groove in an insulating layer along an edge of a first electrode, the thickness of a first charge transport layer is reduced to inhibit leakage current between adjacent pixels.
    Type: Application
    Filed: February 14, 2013
    Publication date: September 12, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Nobuaki Kakinuma, Seishi Miura, Koichi Ishige, Nobuhiko Sato