Abstract: A configuration of a display device capable of color display is obtained. The display device includes a plurality of rod-shaped light-emitting elements each of which includes a semiconductor and which emit light beams having wavelength distributions different from each other, and alignment electrodes (12). The alignment electrodes (12) include a first electrode pair (12a), a second electrode pair (12b), and a third electrode pair (12c).

Abstract: A configuration of a display device capable of color display is obtained. The display device includes a plurality of rod-shaped light-emitting elements each of which includes a semiconductor and which emit light beams having wavelength distributions different from each other, and alignment electrodes (12). The alignment electrodes (12) include a first electrode pair (12a), a second electrode pair (12b), and a third electrode pair (12c).

Abstract: According to this GaN-based HFET, resistivity ? of a semi-insulating film forming a gate insulating film is 3.9×109?cm. The value of this resistivity ? is a value derived when the current density is 6.25×10?4 (A/cm2). By inclusion of the gate insulating film by a semi-insulating film having a resistivity ?=3.9×109?cm, a withstand voltage of 1000 V can be obtained. Meanwhile, the withstand voltage abruptly drops as the resistivity of the gate insulating film exceeds 1 ×1011?cm, and the gate leak current increases when the resistivity of the gate insulating film drops below 1 ×107?cm.

Abstract: A nitride semiconductor layered body includes a Si substrate having a surface, as the principal surface, inclined at an off-angle of 0 degrees or more and 4.0 degrees or less with respect to a plane and a nitride semiconductor layer disposed on the Si substrate.

Abstract: According to this GaN-based HFET, resistivity ? of a semi-insulating film forming a gate insulating film is 3.9×109 ?cm. The value of this resistivity ? is a value derived when the current density is 6.25×10?4 (A/cm2). By inclusion of the gate insulating film by a semi-insulating film having a resistivity ?=3.9×109 ?cm, a withstand voltage of 1000 V can be obtained. Meanwhile, the withstand voltage abruptly drops as the resistivity of the gate insulating film exceeds 1×1011 ?cm, and the gate leak current increases when the resistivity of the gate insulating film drops below 1×107 ?cm.

Abstract: A semiconductor device includes a first transistor of a normally-off type, a second transistor of a normally-on type, and a third transistor of a normally-on type. The first transistor and the second transistor are connected to each other in cascode. The third transistor is connected in parallel with the second transistor. Each of the second transistor and the third transistor has an off-state breakdown voltage higher than an off-state breakdown voltage of the first transistor. The third transistor has a turn-on time shorter than a turn-on time of the second transistor.

Abstract: An epitaxial wafer for a heterojunction type FET includes an AlN primary layer, a stepwisely composition-graded buffer layer structure, a superlattice buffer layer structure, a GaN channel layer, and a nitride semiconductor electron supply layer, which are sequentially provided on a Si substrate, the stepwisely composition-graded buffer layer structure including a plurality of AlGaN buffer layers provided on each other such that an Al composition ratio is sequentially reduced, an uppermost layer thereof having a composition of AlxGa1?xN (0<x), a plurality of sets of an AlyGa1?yN (y?1) superlattice constituting layer and an AlzGa1?zN (0<z<y) superlattice constituting layer being provided on each other alternately starting from one of the AlyGa1?yN superlattice constituting layer and the AlzGa1?zN superlattice constituting layer in the superlattice buffer layer structure, the AlxGa1?xN buffer layer and the AlzGa1?zN superlattice constituting layer satisfying x?0.05?z?x+0.05.

Abstract: A group III nitride semiconductor multilayer substrate (100) includes a channel layer (5) which is a group III nitride semiconductor, a barrier layer (6) which is formed on the channel layer (5) to form a heterointerface in combination with the channel layer (5) and which is a group III nitride semiconductor, wherein in the barrier layer (6, 206), a Cu concentration in a region of 10 nm or less depths from its surface is 1.0×1010 (atomicity/cm2) or less.

Abstract: A nitride semiconductor growth apparatus of the present invention comprises a chamber into which a reactive gas containing nitrogen is to be introduced as a material gas and a reaction part which is placed in the chamber and in which the material gas is brought into reaction to grow a nitride semiconductor. In the nitride semiconductor growth apparatus, in a region which includes a reaction part and part of an upstream side from a reaction part with respect to a flow of a material gas, portions to be in contact with the material gas (a gas introducing part, a current introducing part and a view port part and the like) are made from non-copper material (i.e., material containing no copper).

Abstract: An epitaxial wafer for a heterojunction type FET includes an AlN primary layer, a stepwisely composition-graded buffer layer structure, a superlattice buffer layer structure, a GaN channel layer, and a nitride semiconductor electron supply layer, which are sequentially provided on a Si substrate, the stepwisely composition-graded buffer layer structure including a plurality of AlGaN buffer layers provided on each other such that an Al composition ratio is sequentially reduced, an uppermost layer thereof having a composition of AlxGa1—xN (0<x), a plurality of sets of an AlyGa1?yN (y?1) superlattice constituting layer and an AlzGa1?zN (0<z<y) superlattice constituting layer being provided on each other alternately starting from one of the AlyGa1?yN superlattice constituting layer and the AlzGa1?zN superlattice constituting layer in the superlattice buffer layer structure, the AlxGa1?xN buffer layer and the AlzGa1?zN superlattice constituting layer satisfying x?0.05?z?x+0.05.

Abstract: An epitaxial wafer including nitride-based semiconductor layers usable for a hetero-junction field effect type transistor, includes a first buffer layer of AlN or AlON, a second buffer layer of AlxGa1-xN having its Al composition ratios decreased in a stepwise fashion, a third buffer layer including a multilayer of repeatedly stacked AlaGa1-aN layers/AlbGa1-bN layers disposed on the second buffer layer, a GaN channel layer, and an electron supply layer in this order on a Si substrate, wherein the Al composition ratio x in the uppermost part of the second buffer layer is in a range of 0?x?0.3.

Abstract: There is provided a hetero junction field effect transistor including: a first layer of a nitride based, group III-V compound semiconductor; a second layer of a nitride based, group III-V compound semiconductor containing a rare earth element, overlying the first layer; a pair of third layers of a nitride based, group III-V compound semiconductor, overlying the second layer, the third layers being spaced from each other; a gate electrode disposed between the third layers at least a region of the second layer; and a source electrode overlying one of the third layers and a drain electrode overlying an other of the third layers. A method of fabricating the hetero junction field effect transistor is also provided.

Abstract: There is provided a field effect transistor of a normally-OFF operation having a low contact resistance and capable of avoiding increases in on-resistance and maintaining high channel mobility. In this field effect transistor, a thin-layer portion 6a of an AlGaN barrier layer 6, which is formed on V defects 13 of a second GaN layer 4 and on non-grown regions G1 of a third GaN layer 5 adjoining the V defects 13, can be made thinner than a flat portion 6b without etching. Therefore, increases in the on-resistance can be avoided without causing degradation of the channel mobility due to etching damage.

Abstract: There is provided a hetero junction field effect transistor including: a first layer of a nitride based, group III-V compound semiconductor; a second layer of a nitride based, group III-V compound semiconductor containing a rare earth element, overlying the first layer; a pair of third layers of a nitride based, group III-V compound semiconductor, overlying the second layer, the third layers being spaced from each other; a gate electrode disposed between the third layers at least a region of the second layer; and a source electrode overlying one of the third layers and a drain electrode overlying an other of the third layers. A method of fabricating the hetero junction field effect transistor is also provided.

Abstract: There is provided a hetero junction field effect transistor including: a first layer of a nitride based, group III-V compound semiconductor; a second layer of a nitride based, group III-V compound semiconductor containing a rare earth element, overlying the first layer; a pair of third layers of a nitride based, group III-V compound semiconductor, overlying the second layer, the third layers being spaced from each other; a gate electrode disposed between the third layers at least a region of the second layer; and a source electrode overlying one of the third layers and a drain electrode overlying an other of the third layers. A method of fabricating the hetero junction field effect transistor is also provided.

Abstract: A nitride-based group III-V compound semiconductor device includes a buffer layer, a first nitride semiconductor layer and a second nitride semiconductor layer successively stacked on a substrate, the first and the second nitride layers having their respective lattice constants a1 and a2 in the relation a1>a2, an ohmic source electrode and an ohmic drain electrode formed on the second nitride layer, and a piezoelectric effect film formed on at least a partial region between the electrodes, wherein the piezoelectric film exerts compressive stress of an absolute magnitude at least equivalent to that of tensile stress applied to the second nitride layer due to the difference (a1?a2) between the lattice constants of the first and second nitride layers.

Abstract: A field-effect transistor is provided which includes: a first nitride semiconductor layer having a lattice constant a1 and a bandgap Eg1; a second nitride semiconductor layer stacked on the first nitride semiconductor layer and having a lattice constant a2 and a bandgap Eg2; a source electrode and a drain electrode formed on the second nitride semiconductor layer; a piezo-effect film formed on the second nitride semiconductor layer in a region between the source electrode and the drain electrode; and a gate electrode formed on a region of the piezo-effect film. The relation between the lattice constants a1 and a2 is a1>a2. The relation between the bandgaps Eg1 and Eg2 is Eg1<Eg2.

Abstract: There is provided a hetero junction field effect transistor including: a first layer of a nitride based, group III-V compound semiconductor; a second layer of a nitride based, group III-V compound semiconductor containing a rare earth element, overlying the first layer; a pair of third layers of a nitride based, group III-V compound semiconductor, overlying the second layer, the third layers being spaced from each other; a gate electrode disposed between the third layers at least a region of the second layer; and a source electrode overlying one of the third layers and a drain electrode overlying an other of the third layers. A method of fabricating the hetero junction field effect transistor is also provided.

Abstract: A field-effect transistor is provided which includes: a first nitride semiconductor layer having a lattice constant a1 and a bandgap Eg1; a second nitride semiconductor layer stacked on the first nitride semiconductor layer and having a lattice constant a2 and a bandgap Eg2; a source electrode and a drain electrode formed on the second nitride semiconductor layer; a piezo-effect film formed on the second nitride semiconductor layer in a region between the source electrode and the drain electrode; and a gate electrode formed on a region of the piezo-effect film. The relation between the lattice constants a1 and a2 is a1>a2. The relation between the bandgaps Eg1 and Eg2 is Eg1<Eg2.

Abstract: An electrode employing a nitride-based semiconductor of III–V group compound having a favorable ohmic characteristic and a producing method thereof are provided. The electrode includes a nitride-based semiconductor layer of III–V group compound, an electrode metal, and a metal oxide inserted therebetween. The metal oxide is preferably an oxide of metal element(s) permitting formation of a nitride semiconductor.