Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.

Abstract: Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.