Patents by Inventor Nobuhiko Honda

Nobuhiko Honda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11221789
    Abstract: When a plurality of write data is merged to generate a code for protecting data stored in the main memory, the write data is protected in the memory controller. A first code generation unit generates a first code based on the write data stored in a first sub memory, and stores the generated first code in a second sub memory. The sub memory controller reads the write data to be merged from the first sub memory, and verifies whether the read write data includes an error by using the first code stored in the second sub memory. When the read write data does not include an error, the sub memory controller merges valid data of the write data read from the first sub memory, and outputs the merged data to a second code generation unit. The second code generation unit generates a second code based on the merged data.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: January 11, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Nobuhiko Honda, Takahiro Irita
  • Patent number: 11188488
    Abstract: Each master issues an access request including a read request and a write request to a memory. A cache caches the write request issued by the master. A central bus control system performs access control for the read request issued by each master and the write request output by the cache. A central bus control system performs access control for the write request issued by each master. The central bus control system performs access control in accordance with a free situation of a buffer of a memory controller. The central bus control system performs access control in accordance with a free situation of the cache.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 30, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki, Nobuhiko Honda
  • Publication number: 20210141749
    Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.
    Type: Application
    Filed: January 15, 2021
    Publication date: May 13, 2021
    Inventors: Katsuya MIZUMOTO, Toshiyuki HIRAKI, Nobuhiko HONDA, Sho YAMANAKA, Takahiro IRITA, Yoshihiko HOTTA
  • Patent number: 10929317
    Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: February 23, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsuya Mizumoto, Toshiyuki Hiraki, Nobuhiko Honda, Sho Yamanaka, Takahiro Irita, Yoshihiko Hotta
  • Publication number: 20200201559
    Abstract: When a plurality of write data is merged to generate a code for protecting data stored in the main memory, the write data is protected in the memory controller. A first code generation unit generates a first code based on the write data stored in a first sub memory, and stores the generated first code in a second sub memory. The sub memory controller reads the write data to be merged from the first sub memory, and verifies whether the read write data includes an error by using the first code stored in the second sub memory. When the read write data does not include an error, the sub memory controller merges valid data of the write data read from the first sub memory, and outputs the merged data to a second code generation unit. The second code generation unit generates a second code based on the merged data.
    Type: Application
    Filed: November 15, 2019
    Publication date: June 25, 2020
    Inventors: Sho YAMANAKA, Nobuhiko HONDA, Takahiro IRITA
  • Publication number: 20190196997
    Abstract: Each master issues an access request including a read request and a write request to a memory. A cache caches the write request issued by the master. A central bus control system performs access control for the read request issued by each master and the write request output by the cache. A central bus control system performs access control for the write request issued by each master. The central bus control system performs access control in accordance with a free situation of a buffer of a memory controller. The central bus control system performs access control in accordance with a free situation of the cache.
    Type: Application
    Filed: November 13, 2018
    Publication date: June 27, 2019
    Inventors: Sho YAMANAKA, Toshiyuki HIRAKI, Nobuhiko HONDA
  • Publication number: 20190004983
    Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.
    Type: Application
    Filed: June 5, 2018
    Publication date: January 3, 2019
    Inventors: Katsuya Mizumoto, Toshiyuki Hiraki, Nobuhiko Honda, Sho Yamanaka, Takahiro Irita, Yoshihiko Hotta
  • Patent number: 10090028
    Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: October 2, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Junkei Sato, Nobuhiko Honda
  • Publication number: 20170236569
    Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Inventors: Junkei Sato, Nobuhiko Honda
  • Patent number: 9691449
    Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: June 27, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Junkei Sato, Nobuhiko Honda
  • Publication number: 20150310899
    Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.
    Type: Application
    Filed: July 7, 2015
    Publication date: October 29, 2015
    Inventors: Junkei Sato, Nobuhiko Honda
  • Patent number: 9111632
    Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 18, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Junkei Sato, Nobuhiko Honda
  • Publication number: 20130124795
    Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.
    Type: Application
    Filed: June 21, 2011
    Publication date: May 16, 2013
    Inventors: Junkei Sato, Nobuhiko Honda
  • Patent number: 5122693
    Abstract: Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.
    Type: Grant
    Filed: November 13, 1990
    Date of Patent: June 16, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuhiko Honda, Toyohiko Yoshida, Yukihiko Shimazu
  • Patent number: D735920
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: August 4, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Nobuhiko Honda
  • Patent number: D782088
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: March 21, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Nobuhiko Honda
  • Patent number: D796090
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: August 29, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Nobuhiko Honda, Koichi Matsumoto
  • Patent number: D938309
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: December 14, 2021
    Inventors: Nobuhiko Honda, Pansoo Kwon, Hideo Koyama, Daisuke Iguchi