Patents by Inventor Nobuhiko Nishiyama
Nobuhiko Nishiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11946879Abstract: A thin film has a band gap of 2.2 eV or more and in which a crystal includes an atomic vacancy and an electron, a microwave irradiation system configured to irradiate the thin film with a microwave in response to driving from outside, an excitation unit configured to excite the electron included in the thin film in response to driving from outside, and a detector configured to detect, as an electric signal, at least either one of an intensity of light outputted from the thin film when the electron transitions from an excited state to a ground state and a change in conductivity of the thin film based on excitation.Type: GrantFiled: September 13, 2019Date of Patent: April 2, 2024Assignee: TOKYO INSTITUTE OF TECHNOLOGYInventors: Mutsuko Hatano, Takayuki Iwasaki, Nobuhiko Nishiyama, Yuta Masuyama, Takuya Murooka
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Publication number: 20230060877Abstract: A semiconductor optical device includes a substrate having an optical waveguide, a gain section formed of a compound semiconductor having an optical gain and bonded to an upper surface of the substrate, the gain section having a first mesa, and a first wiring line electrically connected to the gain section. The first mesa of the gain section is optically coupled to the optical waveguide. The substrate includes a first layer, a second layer, and a third layer. The first layer has a higher thermal conductivity than the second layer. The second layer is stacked on the first layer. The third layer is stacked on the second layer. A recess provided in the substrate extends through the third layer to the second layer in the thickness direction. The first wiring line extends from the first mesa of the gain section to the recess.Type: ApplicationFiled: August 29, 2022Publication date: March 2, 2023Applicant: Sumitomo Electric Industries, Ltd.Inventors: Naoko KONISHI, Takehiko KIKUCHI, Hideki YAGI, Nobuhiko NISHIYAMA
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Patent number: 11448729Abstract: In a light deflection device and a lidar device, a parallel operation can be realized with a simple constitution, so as to avoid enlargement or complication of a system. The reflection angle of the light deflection device depends on a wavelength and a refractive index, so that light beams with respective wavelengths different from each other are simultaneously and parallelly deflected in directions of deflection angles each defined by the wavelength and the refractive index. The light beams with the plural wavelengths different from each other are deflected at the different deflection angles each defined by each wavelength and the refractive index, so that they can be deflected simultaneously and parallelly. The plural deflected light beams can be distinguished from each other based on the difference in the wavelength and the deflection angle of the light, even in the simultaneous and parallel operation.Type: GrantFiled: June 28, 2017Date of Patent: September 20, 2022Assignees: NATIONAL UNIVERSITY CORPORATION YOKOHAMA NATIONAL UNIVERSITY, TOKYO INSTITUTE OF TECHNOLOGYInventors: Toshihiko Baba, Nobuhiko Nishiyama
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Publication number: 20220278503Abstract: A method of manufacturing a semiconductor optical device includes a step of bonding a semiconductor element to a substrate that includes silicon, the semiconductor element being made of a III-V compound semiconductor and having optical gain; after the step of bonding the semiconductor element, a step of molding the semiconductor element by wet-etching; and after the step of molding the semiconductor element, a step of forming a mesa at the semiconductor element. The substrate includes a waveguide, a groove that extends along the waveguide, a terrace that is positioned on a side of the groove opposite to the waveguide, and a wall that covers the groove. The step of bonding the semiconductor element is a step of bonding the semiconductor element to the waveguide, the groove, the terrace, and the wall of the substrate.Type: ApplicationFiled: February 8, 2022Publication date: September 1, 2022Applicant: Sumitomo Electric Industries, Ltd.Inventors: Takehiko KIKUCHI, Naoki FUJIWARA, Nobuhiko NISHIYAMA
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Patent number: 11270907Abstract: A method for producing a semiconductor device includes a step of bonding a chip to a SOI wafer, the chip being formed of a III-V group compound semiconductor and including a substrate and a first semiconductor layer; and a step of removing the substrate and the first semiconductor layer from the chip after the step of bonding. In the producing method, the first semiconductor layer has a tensile strain, and the SOI wafer and the chip are heated to a first temperature in the step of bonding, and are cooled to a second temperature lower than the first temperature after the step of bonding.Type: GrantFiled: August 21, 2020Date of Patent: March 8, 2022Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takehiko Kikuchi, Hideki Yagi, Nobuhiko Nishiyama
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Publication number: 20220057338Abstract: A thin film has a band gap of 2.2 eV or more and in which a crystal includes an atomic vacancy and an electron, a microwave irradiation system configured to irradiate the thin film with a microwave in response to driving from outside, an excitation unit configured to excite the electron included in the thin film in response to driving from outside, and a detector configured to detect, as an electric signal, at least either one of an intensity of light outputted from the thin film when the electron transitions from an excited state to a ground state and a change in conductivity of the thin film based on excitation.Type: ApplicationFiled: September 13, 2019Publication date: February 24, 2022Applicant: TOKYO INSTITUTE OF TECHNOLOGYInventors: Mutsuko HATANO, Takayuki IWASAKI, Nobuhiko NISHIYAMA, Yuta MASUYAMA, Takuya MUROOKA
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Patent number: 11056341Abstract: A method of manufacturing an optical semiconductor element includes: stacking a plurality of compound semiconductor layers on a first substrate containing a compound semiconductor; dividing the first substrate into small pieces; forming terraces, grooves, walls, and a first mesa for a waveguide on a second substrate containing silicon; jointing at least one small piece to the second substrate after the forming; wet-etching the first substrate so as to expose the compound semiconductor layers after the jointing; and forming a second mesa opposite to the first mesa from the compound semiconductor layers; wherein the grooves are formed on both sides of the first mesa, the terraces are formed on both sides of the first mesa and the grooves, and the walls are arranged in an extending direction of each groove.Type: GrantFiled: September 16, 2019Date of Patent: July 6, 2021Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takehiko Kikuchi, Morihiro Seki, Nobuhiko Nishiyama
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Publication number: 20210066117Abstract: A method for producing a semiconductor device includes a step of bonding a chip to a SOI wafer, the chip being formed of a III-V group compound semiconductor and including a substrate and a first semiconductor layer; and a step of removing the substrate and the first semiconductor layer from the chip after the step of bonding. In the producing method, the first semiconductor layer has a tensile strain, and the SOI wafer and the chip are heated to a first temperature in the step of bonding, and are cooled to a second temperature lower than the first temperature after the step of bonding.Type: ApplicationFiled: August 21, 2020Publication date: March 4, 2021Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takehiko KIKUCHI, Hideki YAGI, Nobuhiko NISHIYAMA
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Publication number: 20200365445Abstract: A susceptor includes a first metal plate and a second metal plate bonded to a surface of the first metal plate. The second metal plate has a plurality of first openings. The surface of the first metal plate is exposed from the plurality of first openings.Type: ApplicationFiled: April 27, 2020Publication date: November 19, 2020Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takehiko KIKUCHI, Nobuhiko NISHIYAMA
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Publication number: 20200098567Abstract: A method of manufacturing an optical semiconductor element includes: stacking a plurality of compound semiconductor layers on a first substrate containing a compound semiconductor; dividing the first substrate into small pieces; forming terraces, grooves, walls, and a first mesa for a waveguide on a second substrate containing silicon; jointing at least one small piece to the second substrate after the forming; wet-etching the first substrate so as to expose the compound semiconductor layers after the jointing; and forming a second mesa opposite to the first mesa from the compound semiconductor layers; wherein the grooves are formed on both sides of the first mesa, the terraces are formed on both sides of the first mesa and the grooves, and the walls are arranged in an extending direction of each groove.Type: ApplicationFiled: September 16, 2019Publication date: March 26, 2020Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takehiko Kikuchi, Morihiro Seki, Nobuhiko Nishiyama
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Patent number: 10490684Abstract: A compound photovoltaic cell includes a substrate, a first cell made of a first semiconductor material and formed on the substrate, a tunnel layer, and a second cell made of a second semiconductor material lattice mismatched with a material of the substrate, connected to the first cell via the tunnel layer, and disposed on an incident side with respect to the first cell, wherein band gaps of the first and the second cells become smaller from an incident side to a back side, and wherein the tunnel layer includes a p-type layer disposed on the incident side and a n-type layer disposed on the back side, the p-type layer being a p+-type (Al)GaInAs layer, the n-type layer being an n+-type InP layer, an n+-type GaInP layer having a tensile strain with respect to InP or n+-type Ga(In)PSb layer having a tensile strain with respect to InP.Type: GrantFiled: April 10, 2017Date of Patent: November 26, 2019Assignee: RICOH COMPANY, LTD.Inventors: Shunichi Sato, Nobuhiko Nishiyama
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Publication number: 20190204419Abstract: In a light deflection device and a lider device, a parallel operation can be realized with a simple constitution, so as to avoid enlargement or complication of a system. The reflection angle of the light deflection device depends on a wavelength and a refractive index, so that light beams with respective wavelengths different from each other are simultaneously and parallelly deflected in directions of deflection angles each defined by the wavelength and the refractive index. The light beams with the plural wavelengths different from each other are deflected at the different deflection angles each defined by each wavelength and the refractive index, so that they can be deflected simultaneously and parallelly. The plural deflected light beams can be distinguished from each other based on the difference in the wavelength and the deflection angle of the light, even in the simultaneous and parallel operation.Type: ApplicationFiled: June 28, 2017Publication date: July 4, 2019Applicants: NATIONAL UNIVERSITY CORPORATION YOKOHAMA NATIONAL UNIVERSITY, TOKYO INSTITUTE OF TECHNOLOGYInventors: Toshihiko BABA, Nobuhiko NISHIYAMA
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Patent number: 10008627Abstract: A photovoltaic cell manufacturing method includes depositing a first buffer layer for performing lattice relaxation on a first silicon substrate; depositing a first photoelectric conversion cell on the first buffer layer, the first photoelectric conversion cell being formed with a compound semiconductor including a pn junction, and the first photoelectric conversion cell having a lattice constant that is higher than that of silicon; connecting a support substrate to the first photoelectric conversion cell to form a first layered body; and removing the first buffer layer and the first silicon substrate from the first layered body.Type: GrantFiled: August 5, 2016Date of Patent: June 26, 2018Assignee: RICOH COMPANY, LTD.Inventors: Shunichi Sato, Nobuhiko Nishiyama
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Publication number: 20170213932Abstract: A compound photovoltaic cell includes a substrate, a first cell made of a first semiconductor material and formed on the substrate, a tunnel layer, and a second cell made of a second semiconductor material lattice mismatched with a material of the substrate, connected to the first cell via the tunnel layer, and disposed on an incident side with respect to the first cell, wherein band gaps of the first and the second cells become smaller from an incident side to a back side, and wherein the tunnel layer includes a p-type layer disposed on the incident side and a n-type layer disposed on the back side, the p-type layer being a p+-type (Al)GaInAs layer, the n-type layer being an n+-type InP layer, an n+-type GaInP layer having a tensile strain with respect to InP or n+-type Ga(In)PSb layer having a tensile strain with respect to InP.Type: ApplicationFiled: April 10, 2017Publication date: July 27, 2017Applicant: RICOH COMPANY, LTD.Inventors: Shunichi SATO, Nobuhiko Nishiyama
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Publication number: 20160343898Abstract: A photovoltaic cell manufacturing method includes depositing a first buffer layer for performing lattice relaxation on a first silicon substrate; depositing a first photoelectric conversion cell on the first buffer layer, the first photoelectric conversion cell being formed with a compound semiconductor including a pn junction, and the first photoelectric conversion cell having a lattice constant that is higher than that of silicon; connecting a support substrate to the first photoelectric conversion cell to form a first layered body; and removing the first buffer layer and the first silicon substrate from the first layered body.Type: ApplicationFiled: August 5, 2016Publication date: November 24, 2016Applicant: RICOH COMPANY, LTD.Inventors: Shunichi SATO, Nobuhiko Nishiyama
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Patent number: 9450138Abstract: A photovoltaic cell manufacturing method includes depositing a first buffer layer for performing lattice relaxation on a first silicon substrate; depositing a first photoelectric conversion cell on the first buffer layer, the first photoelectric conversion cell being formed with a compound semiconductor including a pn junction, and the first photoelectric conversion cell having a lattice constant that is higher than that of silicon; connecting a support substrate to the first photoelectric conversion cell to form a first layered body; and removing the first buffer layer and the first silicon substrate from the first layered body.Type: GrantFiled: November 25, 2013Date of Patent: September 20, 2016Assignee: RICOH COMPANY, LTD.Inventors: Shunichi Sato, Nobuhiko Nishiyama
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Publication number: 20150333214Abstract: A photovoltaic cell manufacturing method includes depositing a first buffer layer for performing lattice relaxation on a first silicon substrate; depositing a first photoelectric conversion cell on the first buffer layer, the first photoelectric conversion cell being formed with a compound semiconductor including a pn junction, and the first photoelectric conversion cell having a lattice constant that is higher than that of silicon; connecting a support substrate to the first photoelectric conversion cell to form a first layered body; and removing the first buffer layer and the first silicon substrate from the first layered body.Type: ApplicationFiled: November 25, 2013Publication date: November 19, 2015Applicant: RICOH COMPANY, LTD.Inventors: Shunichi SATO, Nobuhiko NISHIYAMA
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Publication number: 20150034153Abstract: A compound photovoltaic cell includes a substrate, a first cell made of a first semiconductor material and formed on the substrate, a tunnel layer, and a second cell made of a second semiconductor material lattice mismatched with a material of the substrate, connected to the first cell via the tunnel layer, and disposed on an incident side with respect to the first cell, wherein band gaps of the first and the second cells become smaller from an incident side to a back side, and wherein the tunnel layer includes a p-type layer disposed on the incident side and a n-type layer disposed on the back side, the p-type layer being a p+-type (Al)GaInAs layer, the n-type layer being an n+-type InP layer, an n+-type GaInP layer having a tensile strain with respect to InP or n+-type Ga(In)PSb layer having a tensile strain with respect to InP.Type: ApplicationFiled: July 29, 2014Publication date: February 5, 2015Applicant: RICOH COMPANY, LTD.Inventors: Shunichi Sato, Nobuhiko Nishiyama
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Patent number: 7502394Abstract: Both a system and method are provided for modulating the intensity of an output beam generated by semiconductor laser. The exemplary system includes a source of pulsating current connected to the laser that generates a pulsating beam of laser light, an external modulator having an input that receives the pulsating beam, and an output controlled by pulsating control signal, wherein the output beam transmitted by the external modulator output is modulated by changing a relative phase angle between the pulsating current powering the laser, and the control signal of the external modulator over time. The external modulator may be an intensity-type modulator whose output is controlled by a gate signal having a constant phase, and the source of pulsating current powering the laser may be variable phase in order to modulate the output beam with an external modulator having a simple structure.Type: GrantFiled: December 8, 2005Date of Patent: March 10, 2009Assignee: Corning IncorporatedInventors: Martin H Hu, Nobuhiko Nishiyama, Chung-En Zah
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Patent number: 7400659Abstract: The present invention is directed to a method and system for providing a three-level current scheme to a semiconductor laser to control beam wavelength and laser temperature. A first current is received into a gain section of the semiconductor laser and at least one other current is received into a DBR and/or phase section of the semiconductor laser. This other current(s) is pulse-width modulated based upon a required temperature value. An output beam is generated by the semiconductor laser based upon the received first current and the received pulse-width modulated current(s).Type: GrantFiled: December 8, 2005Date of Patent: July 15, 2008Assignee: Corning IncorporatedInventors: Martin H Hu, Nobuhiko Nishiyama, Chung-En Zah