Patents by Inventor Nobuhiro Imaizumi

Nobuhiro Imaizumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8673762
    Abstract: A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Limited
    Inventors: Toshiya Akamatsu, Nobuhiro Imaizumi, Seiki Sakuyama, Keisuke Uenishi, Tetsuhiro Nakanishi
  • Patent number: 8674520
    Abstract: A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Limited
    Inventors: Nobuhiro Imaizumi, Keishiro Okamoto, Keiji Watanabe
  • Patent number: 8492784
    Abstract: A semiconductor device includes: a semiconductor chip including a nitride semiconductor layered structure including a carrier transit layer and a carrier supply layer; a first resin layer on the semiconductor chip, the first resin layer including a coupling agent; a second resin layer on the first resin layer, the second resin layer including a surfactant; and a sealing resin layer to seal the semiconductor chip with the first resin layer and the second resin layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 23, 2013
    Assignee: Fujitsu Limited
    Inventors: Keishiro Okamoto, Tadahiro Imada, Nobuhiro Imaizumi, Keiji Watanabe
  • Patent number: 8409931
    Abstract: A method of manufacturing a semiconductor device includes: forming a first layer including crystals by processing a surface of a first electrode of a semiconductor element; forming a second layer including crystals by processing a surface of a second electrode of a mounting member on which the semiconductor element is mounted; reducing a first oxide film present over or in the first layer and a second oxide film present over or in the second layer at a first temperature, the first temperature being lower than a second temperature at which a first metal included in the first electrode diffuses in a solid state and being lower than a third temperature at which a second metal included in the second electrode diffuses in a solid state; and bonding the first layer and the second layer to each other by solid-phase diffusion.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Limited
    Inventors: Taiji Sakai, Nobuhiro Imaizumi, Masataka Mizukoshi
  • Publication number: 20120244665
    Abstract: A method of manufacturing a semiconductor device includes: forming a first layer including crystals by processing a surface of a first electrode of a semiconductor element; forming a second layer including crystals by processing a surface of a second electrode of a mounting member on which the semiconductor element is mounted; reducing a first oxide film present over or in the first layer and a second oxide film present over or in the second layer at a first temperature, the first temperature being lower than a second temperature at which a first metal included in the first electrode diffuses in a solid state and being lower than a third temperature at which a second metal included in the second electrode diffuses in a solid state; and bonding the first layer and the second layer to each other by solid-phase diffusion.
    Type: Application
    Filed: February 24, 2012
    Publication date: September 27, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Taiji SAKAI, Nobuhiro Imaizumi, Masataka Mizukoshi
  • Publication number: 20120217626
    Abstract: A method for manufacturing a semiconductor device, includes: placing a seal layer including a connection conductive film on the surface so that the connection conductive film is in contact with an electrode of a semiconductor element and a lead; electrically coupling the electrode and the lead through the connection conductive film; and sealing the semiconductor element by the seal layer.
    Type: Application
    Filed: January 19, 2012
    Publication date: August 30, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Taiji SAKAI, Kazukiyo Joshin, Tadahiro Imada, Nobuhiro Imaizumi, Keishiro Okamoto
  • Publication number: 20120211762
    Abstract: A semiconductor device includes: a semiconductor chip having an electrode; a lead corresponding to the electrode; a metal line coupling the electrode to the lead; a first resin portion covering a coupling portion between the metal line and the electrode and a coupling portion between the metal line and the lead; and a second resin portion covering the metal line, the first resin portion, and the semiconductor chip.
    Type: Application
    Filed: December 22, 2011
    Publication date: August 23, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Tadahiro IMADA, Keishiro Okamoto, Nobuhiro Imaizumi, Toshihide Kikkawa
  • Publication number: 20120211901
    Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.
    Type: Application
    Filed: January 23, 2012
    Publication date: August 23, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Kozo SHIMIZU, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada, Keiji Watanabe
  • Publication number: 20120211899
    Abstract: A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.
    Type: Application
    Filed: January 23, 2012
    Publication date: August 23, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Nobuhiro IMAIZUMI, Keishiro Okamoto, Keiji Watanabe
  • Publication number: 20120211764
    Abstract: A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 23, 2012
    Applicant: FUJITSU LIMITED,
    Inventors: Keishiro OKAMOTO, Tadahiro IMADA, Nobuhiro IMAIZUMI, Keiji WATANABE
  • Publication number: 20120199991
    Abstract: A semiconductor device includes: a semiconductor chip including a nitride semiconductor layered structure including a carrier transit layer and a carrier supply layer; a first resin layer on the semiconductor chip, the first resin layer including a coupling agent; a second resin layer on the first resin layer, the second resin layer including a surfactant; and a sealing resin layer to seal the semiconductor chip with the first resin layer and the second resin layer.
    Type: Application
    Filed: December 20, 2011
    Publication date: August 9, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Keishiro OKAMOTO, Tadahiro Imada, Nobuhiro Imaizumi, Keiji Watanabe
  • Publication number: 20120193800
    Abstract: A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.
    Type: Application
    Filed: December 7, 2011
    Publication date: August 2, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Toshiya Akamatsu, Nobuhiro Imaizumi, Seiki Sakuyama, Keisuke Uenishi, Tetsuhiro Nakanishi
  • Patent number: 7852439
    Abstract: The invention relates to a multi-layer display element configured by a plurality of layers for use as a display section of electronic paper or others, and a manufacturing method for the multi-layer display element. The invention provides a multi-layer display element that allows a pixel area not being narrowed, a high yield of electrode formation, and interlayer connection with no need for a high-temperature process, and a manufacturing method for such a multi-layer display element. The multi-layer liquid crystal display element includes a data signal output terminal group from which data signals are provided, a scanning signal output terminal group from which scanning signals are provided, a data electrode connection wire rod group respectively connecting data electrodes to the data signal output terminal group, and a scanning electrode connection wire rod group respectively connecting scanning electrodes to the scanning signal output terminal group.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: December 14, 2010
    Assignee: Fujitsu Limited
    Inventors: Hisashi Yamaguchi, Fumio Yamagishi, Shigeo Matsunuma, Nobuhiro Imaizumi, Yoshikatsu Ishizuki, Taiji Sakai, Junji Tomita
  • Patent number: 7816180
    Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: October 19, 2010
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
  • Patent number: 7811835
    Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: October 12, 2010
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
  • Publication number: 20100097550
    Abstract: The invention relates to a multi-layer display element configured by a plurality of layers for use as a display section of electronic paper or others, and a manufacturing method for the multi-layer display element. The invention provides a multi-layer display element that allows a pixel area not being narrowed, a high yield of electrode formation, and interlayer connection with no need for a high-temperature process, and a manufacturing method for such a multi-layer display element. The multi-layer liquid crystal display element includes a data signal output terminal group from which data signals are provided, a scanning signal output terminal group from which scanning signals are provided, a data electrode connection wire rod group respectively connecting data electrodes to the data signal output terminal group, and a scanning electrode connection wire rod group respectively connecting scanning electrodes to the scanning signal output terminal group.
    Type: Application
    Filed: September 17, 2009
    Publication date: April 22, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hisashi Yamaguchi, Fumio Yamagishi, Shigeo Matsunuma, Nobuhiro Imaizumi, Yoshikatsu Ishizuki, Taiji Sakai, Junji Tomita
  • Publication number: 20090181497
    Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.
    Type: Application
    Filed: March 12, 2009
    Publication date: July 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
  • Publication number: 20090176331
    Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.
    Type: Application
    Filed: March 12, 2009
    Publication date: July 9, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Masataka MIZUKOSHI, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
  • Patent number: 7514295
    Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: April 7, 2009
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
  • Patent number: 7402461
    Abstract: The present invention is aimed at providing a method of connecting base materials capable of forming metal terminals having a uniform height and smooth surface with a low cost, and of realizing a low-damage mounting, in which a work is planarized while keeping the temperature of the insulating film, possibly elevated due to frictional heat generated during cutting using a cutting tool, lower than 80° C., and keeping the temperature range lower than 80° C. throughout the entire period of the cutting, the electrodes and electrodes are opposed and brought into contact at a temperature of 80° C. or above but lower than the curing temperature of the insulating film, the insulating film is liquefied and a space between the electrodes and electrodes is filled with an insulating resin composing the insulating film, and the insulating resin is cured at the curing temperature or above.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: July 22, 2008
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Taiji Sakai