Patents by Inventor Nobuhiro Kinoshita

Nobuhiro Kinoshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140193954
    Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).
    Type: Application
    Filed: March 11, 2014
    Publication date: July 10, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Naoto Taoka, Atsushi Nakamura, Naozumi Morino, Toshikazu Ishikawa, Nobuhiro Kinoshita
  • Publication number: 20140183759
    Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.
    Type: Application
    Filed: December 23, 2013
    Publication date: July 3, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
  • Patent number: 8701972
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takafumi Nishita, Nobuhiro Kinoshita, Jumpei Konno, Michiaki Sugiyama, Kazunori Hasegawa
  • Patent number: 8698296
    Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: April 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Naoto Taoka, Atsushi Nakamura, Naozumi Morino, Toshikazu Ishikawa, Nobuhiro Kinoshita
  • Publication number: 20140065767
    Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: August 17, 2013
    Publication date: March 6, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Michiaki Sugiyama, Nobuhiro Kinoshita
  • Patent number: 8633103
    Abstract: In order to achieve the highly reliable and highly functional semiconductor device capable of the high-speed transmission by stacking thin chips and substrates, a connecting process and a connecting structure capable of making a solid connection at a low temperature with a low load and maintaining the shape of a connecting portion even if the connecting portion is heated in the stacking process and the subsequent mounting process are provided. In a semiconductor device in which semiconductor chips or wiring boards on which semiconductor chips are mounted are stacked, a connecting structure between electrodes of the stacked semiconductor chips or wiring boards includes a pair of electrodes mainly made of Cu and a solder layer made of Sn—In based alloy sandwiched between the electrodes, and Sn—Cu—Ni intermetallic compounds are dispersed in the solder layer.
    Type: Grant
    Filed: June 13, 2010
    Date of Patent: January 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hanae Hata, Masato Nakamura, Nobuhiro Kinoshita, Jumpei Konno, Chiko Yorita
  • Publication number: 20140004661
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Application
    Filed: August 29, 2013
    Publication date: January 2, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Jumpei KONNO, Takafumi NISHITA, Nobuhiro KINOSHITA, Kazunori HASEGAWA, Michiaki SUGIYAMA
  • Patent number: 8534532
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Grant
    Filed: June 24, 2012
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
  • Publication number: 20130001274
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Application
    Filed: June 24, 2012
    Publication date: January 3, 2013
    Inventors: Jumpei KONNO, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
  • Publication number: 20110012263
    Abstract: In order to achieve the highly reliable and highly functional semiconductor device capable of the high-speed transmission by stacking thin chips and substrates, a connecting process and a connecting structure capable of making a solid connection at a low temperature with a low load and maintaining the shape of a connecting portion even if the connecting portion is heated in the stacking process and the subsequent mounting process are provided. In a semiconductor device in which semiconductor chips or wiring boards on which semiconductor chips are mounted are stacked, a connecting structure between electrodes of the stacked semiconductor chips or wiring boards includes a pair of electrodes mainly made of Cu and a solder layer made of Sn—In based alloy sandwiched between the electrodes, and Sn—Cu—Ni intermetallic compounds are dispersed in the solder layer.
    Type: Application
    Filed: June 13, 2010
    Publication date: January 20, 2011
    Inventors: Hanae HATA, Masato Nakamura, Nobuhiro Kinoshita, Jumpei Konno, Chiko Yorita
  • Publication number: 20100309641
    Abstract: A method of forming narrow-pitch flip-chip bonding electrodes and wire bonding electrodes at the same time is provided so as to reduce the cost of a substrate. In addition, a low-cost solder supply method and a flip-chip bonding method to a thin Au layer are provided. A stacked layer of a Cu layer 23 and a Ni layer 24 is employed as the electrode structure, and an Au layer 25 is plated on the outer periphery thereof. In the flip-chip bonding, dissolution of Au into the solder is minimized by employing a metal jet system in the soldering to the electrodes, so that the formation of Sn—Au having a high melting point is prevented, and at the same time, the wire-bondable Au layer 25 is ensured.
    Type: Application
    Filed: March 21, 2008
    Publication date: December 9, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Hanae Hata, Masato Nakamura, Masaki Nakanishi, Nobuhiro Kinoshita
  • Publication number: 20100301466
    Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).
    Type: Application
    Filed: May 24, 2010
    Publication date: December 2, 2010
    Inventors: Naoto TAOKA, Atsushi Nakamura, Naozumi Morino, Toshikazu Ishikawa, Nobuhiro Kinoshita
  • Publication number: 20100270365
    Abstract: The present invention relates to a solder paste composition used for precoating an electrode surface with solder. A first solder paste composition is contains a solder powder and a flux, and a metallic powder made by metallic species different from metallic species constituting the solder powder and metallic species constituting the electrode surface in a rate of 0.1% by weight or more and 20% by weight or less based on a total amount of the solder powder. When these solder paste compositions are evenly applied onto an electronic circuit substrate for precoating, such a solder that does not generate any swollen portion, solder-lacking portion and variability in a height thereof can be formed irrespective of a shape of a pad.
    Type: Application
    Filed: July 7, 2010
    Publication date: October 28, 2010
    Applicants: Harima Chemicals, Inc., Renesas Technology Corp.
    Inventors: Yoichi KUKIMOTO, Kazuki Ikeda, Hitoshi Sakurai, Nobuhiro Kinoshita, Masaki Nakanishi
  • Patent number: 7732906
    Abstract: There is provided a small and high-performance System in Package (SiP) suitable for high-density mounting. A System in Package (SiP) has a stack structure such that two memory chips are stacked and mounted over the main surface of a wiring substrate, a microcomputer chip is stacked and mounted over the upper part thereof, and the chips are sealed by a mold resin. Each of the memory chips is constructed so as to transmit and receive data to/from the outside of the system via the microcomputer chip. The microcomputer chip is constructed of a multiport structure having various interfaces between it and the outside of the system in addition to an interface between it and the inside of the system. The number of terminals (pins) of the microcomputer chip is much larger than that of the memory chips.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: June 8, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Kuroda, Nobuhiro Kinoshita
  • Patent number: 7598121
    Abstract: A method of manufacturing a semiconductor device includes the steps of: grinding the rear surface of a semiconductor wafer to reduce its thickness; flattening the rear surface of the semiconductor wafer; dividing the semiconductor wafer into a plurality of semiconductor chips; forming gold bumps on the electrodes of the plurality of semiconductor chips; applying NCP to the front surface of a packaging board; and arranging the semiconductor chips over the packaging board through the NCP and pressing the back surfaces of the semiconductor chips to flip-chip bond the semiconductor chips to the packaging board. Therefore, it is possible to prevent NCP from rising onto the back surfaces of the semiconductor chips at the time of flip-chip bonding, whereby separation and cracking caused by a high-temperature treatment for assembly and mounting of a semiconductor device can be prevented and the reliability of the semiconductor device can be improved.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: October 6, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Nobuhiro Kinoshita, Jumpei Konno
  • Patent number: 7504717
    Abstract: There is provided a small and high-performance System in Package (SiP) suitable for high-density mounting. A System in Package (SiP) has a stack structure such that two memory chips are stacked and mounted over the main surface of a wiring substrate, a microcomputer chip is stacked and mounted over the upper part thereof, and the chips are sealed by a mold resin. Each of the memory chips is constructed so as to transmit and receive data to/from the outside of the system via the microcomputer chip. The microcomputer chip is constructed of a multiport structure having various interfaces between it and the outside of the system in addition to an interface between it and the inside of the system. The number of terminals (pins) of the microcomputer chip is much larger than that of the memory chips.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: March 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Kuroda, Nobuhiro Kinoshita
  • Publication number: 20070111384
    Abstract: A method of manufacturing a semiconductor device includes the steps of: grinding the rear surface of a semiconductor wafer to reduce its thickness; flattening the rear surface of the semiconductor wafer; dividing the semiconductor wafer into a plurality of semiconductor chips; forming gold bumps on the electrodes of the plurality of semiconductor chips; applying NCP to the front surface of a packaging board; and arranging the semiconductor chips over the packaging board through the NCP and pressing the back surfaces of the semiconductor chips to flip-chip bond the semiconductor chips to the packaging board. Therefore, it is possible to prevent NCP from rising onto the back surfaces of the semiconductor chips at the time of flip-chip bonding, whereby separation and cracking caused by a high-temperature treatment for assembly and mounting of a semiconductor device can be prevented and the reliability of the semiconductor device can be improved.
    Type: Application
    Filed: January 3, 2007
    Publication date: May 17, 2007
    Inventors: Nobuhiro Kinoshita, Jumpei Konno
  • Patent number: 7214622
    Abstract: In the assembly of a semiconductor device, improvement in the reliability of flip chip bonding is aimed at. By forming a dummy terminal in the end portion of the row of a plurality of terminals for a flip chip in the package substrate, the flow of flux or solder can be suppressed with the dummy terminal, and a solder layer can be formed on the plurality of terminals for a flip chip. Thereby, the thickness of the solder layer formed on each terminal for a flip chip can fully be secured, without making solder adhere to the wire connection terminal closely formed to the terminal for a flip chip. As a result, improvement in the reliability of flip chip bonding can be aimed at.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: May 8, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Michiaki Sugiyama, Nobuhiro Kinoshita, Junpei Konno
  • Publication number: 20060180942
    Abstract: There is provided a small and high-performance System in Package (SiP) suitable for high-density mounting. A System in Package (SiP) has a stack structure such that two memory chips are stacked and mounted over the main surface of a wiring substrate, a microcomputer chip is stacked and mounted over the upper part thereof, and the chips are sealed by a mold resin. Each of the memory chips is constructed so as to transmit and receive data to/from the outside of the system via the microcomputer chip. The microcomputer chip is constructed of a multiport structure having various interfaces between it and the outside of the system in addition to an interface between it and the inside of the system. The number of terminals (pins) of the microcomputer chip is much larger than that of the memory chips.
    Type: Application
    Filed: April 11, 2006
    Publication date: August 17, 2006
    Inventors: Hiroshi Kuroda, Nobuhiro Kinoshita
  • Patent number: 7022732
    Abstract: This invention relates to a medicament containing as an active ingredient, a novel propanolamine having a 1,4-benzodioxane ring or a pharmaceutically acceptable salt thereof: The present compound is represented by the above formula wherein R1-3 may be the same or different and each represents a hydrogen atom, a halogen atom, a hydroxy group, a (C1–C6)alkyl group, a (C1–C6)alkoxy group, a (C1–C6)alkylsulfonamido group, or a phenyl group; R4-5 each represents a hydrogen atom or a (C1–C6)alkyl group; and A represents any of a benzene ring, a pyridine ring and a pyrimidine ring. This compound is useful as a prophylactic or therapeutic agent for diabetes, obesity, hyperlipemia, depression, a respiratory disease, or a gastrointestinal disease.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: April 4, 2006
    Assignees: Nisshin Pharma Inc., Kyorin Pharmaceutical Co., Ltd.
    Inventors: Masahiro Ueno, Koji Kawamura, Makoto Yanai, Toshihiro Takahashi, Nobuhiro Kinoshita, Koichi Katsuyama, Satoko Fuchizawa, Shigeru Hiramoto