Patents by Inventor Nobuhiro Mikami
Nobuhiro Mikami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120073944Abstract: A switch integrated type housing includes a housing body, a switch button sheet, a conductor and a cover sheet. The housing body is provided with a plurality of concave sections on an outer surface of the housing body. The switch button sheet is provided on the outer surface to cover the plurality of concave sections. The conductor has a dome shape downwardly projecting and is provided in each of the plurality of concave sections to contact the switch button sheet. The cover sheet is provided between the switch button sheet and the outer surface of the housing body in a portion of the outer surface of the housing body other than the plurality of concave sections and to cover a lower surface of the conductor in each of the plurality of concave sections.Type: ApplicationFiled: December 6, 2011Publication date: March 29, 2012Applicant: NEC CorporationInventors: Yoshiaki KOBAYASHI, Takaaki YOSHIHIRO, Nobuhiro MIKAMI
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Patent number: 8144482Abstract: A circuit board device includes: plurality of wiring boards (101 and 102) in which terminals are provided on the front and back surfaces and vias are provided for connecting the terminals together, an anisotropic conductive member (103) arranged between wiring boards (101 and 102) for connecting the electrodes of one wiring board to the electrodes of another wiring board, a functional block (104) composed of a metal material and arranged between the wiring boards (101 and 102) to enclose anisotropic conductive member (103), and a pair of holding blocks (105 and 106) composed of a metal material arranged to clamp the plurality of wiring boards (101 and 102), wherein the plurality of wiring boards (101 and 102), while in a state of being clamped between the pair of holding blocks (105 and 106), is connected together by the anisotropic conductive member (103) and the terminals provided on each of the wiring boards (101 and 102), the functional block (104), and the holding blocks (105 and 106) are electrically coType: GrantFiled: May 14, 2007Date of Patent: March 27, 2012Assignee: NEC CorporationInventors: Junya Sato, Toru Taura, Nobuhiro Mikami, Shinji Watanabe, Atsumasa Sawada, Nozomu Nishimura
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Patent number: 8130511Abstract: A circuit board device, a wiring board connecting method, and a circuit board module device are provided for controlling a compression ratio of anisotropically conductive members within an optimal range, for restraining variations in the impact resilient force of the anisotropically conductive members even if an increased number of wiring boards are laminated, for restraining deformations of the wiring board and fluctuations in the impact resilient force of the anisotropically conductive members even if a static external force or the like is applied, for suppressing a linear expansion of the anisotropically conductive members, even if the ambient temperature changes, to increase the stability of electric connections, and for reducing the impact resilient force of the anisotropically conductive members to allow for a reduction in thickness.Type: GrantFiled: May 14, 2007Date of Patent: March 6, 2012Assignee: NEC CorporationInventors: Junya Sato, Nobuhiro Mikami, Shinji Watanabe, Atsumasa Sawada, Nozomu Nishimura
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Patent number: 8119918Abstract: An object of the present invention is to prevent occurrence of an electrical fault such as signal disconnection due to exfoliation between a via and a printed circuit board, via crack, or the like, caused by various stresses that may arise when the printed circuit board is curved. The printed circuit board includes a first wiring layer 11, an electrical insulating base material 12 formed on the first wiring layer 11 and including a via base hole 12a that leads to the first wiring layer 11, and a second wiring layer 16 that is formed on the electrical insulating base material 12 and is electrically connected to the first wiring layer 11 through the via base hole 12a. In a region of the second wiring layer 16 disposed at least in the vicinity of the via base hole 12a, a stress relieving portion 17 is formed which relieves bending stress, tensile stress, compressive stress, and shear stress that may arise when the electrical insulating base material 12 is curved.Type: GrantFiled: September 1, 2006Date of Patent: February 21, 2012Assignee: NEC CorporationInventors: Junya Sato, Shinji Watanabe, Nobuhiro Mikami, Atsumasa Sawada
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Publication number: 20110242780Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.Type: ApplicationFiled: June 10, 2011Publication date: October 6, 2011Applicant: NEC CORPORATIONInventors: Shinji WATANABE, Nobuhiro MIKAMI, Junya SATO, Kenichiro FUJII, Katsumi ABE, Atsumasa SAWADA
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Patent number: 7847389Abstract: Even when a substrate on which a semiconductor package has been mounted is made curved, stress upon electrical connections is mitigated, thereby eliminating faulty connections and improving connection reliability. A semiconductor chip has electrodes on a second face thereof. Support blocks, capable of bending and flexing, are placed at two locations on a peripheral edge of a first face of the semiconductor chip. An interposer is placed so as to span the support blocks with the support blocks interposed between itself and the semiconductor chip, and has a wiring pattern in a flexible resin film. Two end portions of the interposer are folded back onto the side of the second face of the semiconductor chip, and the wiring pattern thereof is electrically connected to the electrodes of the semiconductor chip.Type: GrantFiled: November 13, 2006Date of Patent: December 7, 2010Assignee: NEC CorporationInventors: Nobuhiro Mikami, Shinji Watanabe, Junya Sato, Atsumasa Sawada
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Publication number: 20100148335Abstract: A highly reliable semiconductor package in which faulty connections do not occur even when an external substrate is curved. The semiconductor package includes a semiconductor chip 1; an interposer substrate 10 arranged so as to enclose the semiconductor chip and having a first electrode pad 14, which is for connecting to an electrode of the semiconductor chip, provided on a wiring layer 12 disposed between insulating layers 11, 13; and a first conductor 2 for connecting the electrode of the semiconductor chip and the electrode pad. A portion of the underside of the interposer substrate 10 is adhered to the interposer substrate 10. A gap 4 is provided between the semiconductor chip 1 and the interposer substrate 10 on the side surface of the semiconductor chip 1.Type: ApplicationFiled: May 28, 2007Publication date: June 17, 2010Applicant: NEC CorporationInventors: Nobuhiro Mikami, Shinji Watanabe, Junya Sato, Atsumasa Sawada
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Publication number: 20100126708Abstract: A heat dissipating structure and a portable device are provided, which enable that heat is dissipated from a heat generating part without causing a user to feel discomfort. A heat transfer member is configured to transfer heat generated in a heat generating body and a thermal storrage unit is thermally connected to the heat transfer member. The thermal storrage unit includes a pack with stretching property and a thermal storrage medium which is filled in the pack and a volume of which changes with a change in temperature. The pack is arranged such that there is a gap between the pack and a first heat dissipating portion at normal temperature and the pack contacts the first heat dissipating portion when the thermal storrage medium expands with a change in temperature.Type: ApplicationFiled: January 28, 2008Publication date: May 27, 2010Inventor: Nobuhiro Mikami
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Publication number: 20090266586Abstract: An object of the present invention is to prevent occurrence of an electrical fault such as signal disconnection due to exfoliation between a via and a printed circuit board, via crack, or the like, caused by various stresses that may arise when the printed circuit board is curved. The printed circuit board includes a first wiring layer 11, an electrical insulating base material 12 formed on the first wiring layer 11 and including a via base hole 12a that leads to the first wiring layer 11, and a second wiring layer 16 that is formed on the electrical insulating base material 12 and is electrically connected to the first wiring layer 11 through the via base hole 12a. In a region of the second wiring layer 16 disposed at least in the vicinity of the via base hole 12a, a stress relieving portion 17 is formed which relieves bending stress, tensile stress, compressive stress, and shear stress that may arise when the electrical insulating base material 12 is curved.Type: ApplicationFiled: September 1, 2006Publication date: October 29, 2009Applicant: NEC CORPORATIONInventors: Junya Sato, Shinji Watanabe, Nobuhiro Mikami, Atsumasa Sawada
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Publication number: 20090161331Abstract: A circuit board device, a wiring board connecting method, and a circuit board module device are provided for controlling a compression ratio of anisotropically conductive members within an optimal range, for restraining variations in the impact resilient force of the anisotropically conductive members even if an increased number of wiring boards are laminated, for restraining deformations of the wiring board and fluctuations in the impact resilient force of the anisotropically conductive members even if a static external force or the like is applied, for suppressing a linear expansion of the anisotropically conductive members, even if the ambient temperature changes, to increase the stability of electric connections, and for reducing the impact resilient force of the anisotropically conductive members to allow for a reduction in thickness.Type: ApplicationFiled: May 14, 2007Publication date: June 25, 2009Inventors: Junya Sato, Nobuhiro Mikami, Shinji Watanabe, Atsumasa Sawada, Nozomu Nishimura
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Publication number: 20090135573Abstract: A circuit board device includes: plurality of wiring boards (101 and 102) in which terminals are provided on the front and back surfaces and vias are provided for connecting the terminals together, an anisotropic conductive member (103) arranged between wiring boards (101 and 102) for connecting the electrodes of one wiring board to the electrodes of another wiring board, a functional block (104) composed of a metal material and arranged between the wiring boards (101 and 102) to enclose anisotropic conductive member (103), and a pair of holding blocks (105 and 106) composed of a metal material arranged to clamp the plurality of wiring boards (101 and 102), wherein the plurality of wiring boards (101 and 102), while in a state of being clamped between the pair of holding blocks (105 and 106), is connected together by the anisotropic conductive member (103) and the terminals provided on each of the wiring boards (101 and 102), the functional block (104), and the holding blocks (105 and 106) are electrically coType: ApplicationFiled: May 14, 2007Publication date: May 28, 2009Inventors: Junya Sato, Toru Taura, Nobuhiro Mikami, Shinji Watanabe, Atsumasa Sawada, Nozomu Nishimura
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Publication number: 20090096080Abstract: Even when a substrate on which a semiconductor package has been mounted is made curved, stress upon electrical connections is mitigated, thereby eliminating faulty connections and improving connection reliability. A semiconductor chip has electrodes on a second face thereof. Support blocks, capable of bending and flexing, are placed at two locations on a peripheral edge of a first face of the semiconductor chip. An interposer is placed so as to span the support blocks with the support blocks interposed between itself and the semiconductor chip, and has a wiring pattern in a flexible resin film. Two end portions of the interposer are folded back onto the side of the second face of the semiconductor chip, and the wiring pattern thereof is electrically connected to the electrodes of the semiconductor chip.Type: ApplicationFiled: November 13, 2006Publication date: April 16, 2009Applicant: NEC CORPORATIONInventors: Nobuhiro Mikami, Shinji Watanabe, Junya Sato, Atsumasa Sawada
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Publication number: 20090002973Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.Type: ApplicationFiled: November 8, 2006Publication date: January 1, 2009Applicant: NEC CORPORATIONInventors: Shinji Watanabe, Nobuhiro Mikami, Junya Sato, Kenichiro Fujii, Katsumi Abe, Atsumasa Sawada
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Patent number: 7094985Abstract: A switch integrated type housing includes a housing body, a switch button sheet, a conductor and a cover sheet. The housing body is provided with a plurality of concave sections on an outer surface of the housing body. The switch button sheet is provided on the outer surface to cover the plurality of concave sections. The conductor has a dome shape downwardly projecting and is provided in each of the plurality of concave sections to contact the switch button sheet. The cover sheet is provided between the switch button sheet and the outer surface of the housing body in a portion of the outer surface of the housing body other than the plurality of concave sections and to cover a lower surface of the conductor in each of the plurality of concave sections.Type: GrantFiled: July 7, 2003Date of Patent: August 22, 2006Assignee: NEC CorporationInventors: Yoshiaki Kobayashi, Takaaki Yoshihiro, Nobuhiro Mikami
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Publication number: 20050236265Abstract: A switch integrated type housing includes a housing body, a switch button sheet, a conductor and a cover sheet. The housing body is provided with a plurality of concave sections on an outer surface of the housing body. The switch button sheet is provided on the outer surface to cover the plurality of concave sections. The conductor has a dome shape downwardly projecting and is provided in each of the plurality of concave sections to contact the switch button sheet. The cover sheet is provided between the switch button sheet and the outer surface of the housing body in a portion of the outer surface of the housing body other than the plurality of concave sections and to cover a lower surface of the conductor in each of the plurality of concave sections.Type: ApplicationFiled: July 7, 2003Publication date: October 27, 2005Inventors: Yoshiaki Kobayashi, Takaki Yoshihiro, Nobuhiro Mikami
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Patent number: 5483167Abstract: A ground detecting method for an inverter unit and an apparatus for carrying the method into practice and which zero-phase current is detected on the basis of the output current from the inverter unit. A first value is added whenever the zero-phase current exceeds the ground level. When the added value reaches a predetermined value, it is judged as being the ground level. Further, when the zero-phase current is smaller than the ground level, a second value smaller than the first value, which is added whenever the zero-phase current exceeds the ground level, is subtracted from the added value.Type: GrantFiled: September 8, 1992Date of Patent: January 9, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Nobuhiro Mikami
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Patent number: 5436819Abstract: The present invention provides an apparatus for and a method of compensating an output voltage error of an inverter that changes direct current (DC) power into alternating current (AC) power. More specifically, the present invention provides an apparatus for and a method of compensating for an output voltage error by detecting the polarity of output current from an inverter used to change DC power into AC power. In accordance with one embodiment of the present invention, a current detector is used to detect the output current of the inverter circuit. A polarity discriminating device, receiving the detected output current, sets a threshold current value that is to be used to accurately determine the polarity of the output current. As the output voltage error has the same phase but is opposite in polarity relative to the current output by the inverter, an accurate detection of the output error can be made by accurately detecting the output current polarity.Type: GrantFiled: July 20, 1992Date of Patent: July 25, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Nobuhiro Mikami, Toshio Morohoshi
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Patent number: 5389868Abstract: A drive control apparatus for a driven machine is designed to easily check which of a plurality of parameters indicating the control characteristics of the driven machine have been changed from their factory-set initial values. Initial parameter values are stored in a list in a first memory and current parameter values are stored in a second memory. When a display request is given, the initial values of parameters stored in the first list in a control section are compared to the current values of the parameters stored in nonvolatile memory. The identity of the parameters that have been changed from their initial values are displayed on a liquid crystal display. Also, the stored initial value list is displayed.Type: GrantFiled: February 12, 1993Date of Patent: February 14, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Nobuhiro Mikami, Hisaaki Tsukahara, Hiroshi Yamada, Satomi Yamauchi