Patents by Inventor Nobuhiro Tsuda
Nobuhiro Tsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10734374Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.Type: GrantFiled: August 19, 2019Date of Patent: August 4, 2020Assignee: Renesas Electronics CorporationInventors: Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
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Publication number: 20190378831Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.Type: ApplicationFiled: August 19, 2019Publication date: December 12, 2019Applicant: Renesas Electronics CorporationInventors: Takeshi OKAGAKI, Koji SHIBUTANI, Makoto YABUUCHI, Nobuhiro TSUDA
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Patent number: 10490545Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.Type: GrantFiled: August 6, 2018Date of Patent: November 26, 2019Assignee: Renesas Electronics CorporationInventors: Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
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Publication number: 20180350792Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.Type: ApplicationFiled: August 6, 2018Publication date: December 6, 2018Applicant: Renesas Electronics CorporationInventors: Takeshi OKAGAKI, Koji SHIBUTANI, Makoto YABUUCHI, Nobuhiro TSUDA
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Patent number: 10074651Abstract: A semiconductor device is provided which suppresses variations in transistor characteristics such as a source-drain diffusion capacitance. A first transistor TRA is formed in a first element forming area EFA as a divided transistor. A second transistor TRB is formed in a second element forming area EFB as another divided transistor. The first element forming area EFA and the second element forming area EFB are set to the same size. The first element forming area EFA and the second element forming area EFB are arranged deviated from each other in an X direction by a length SPL corresponding to the minimum pitch PT of a gate wiring GH.Type: GrantFiled: July 24, 2015Date of Patent: September 11, 2018Assignee: Renesas Electronics CorporationInventors: Tetsuya Watanabe, Nobuhiro Tsuda
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Patent number: 10068891Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.Type: GrantFiled: September 29, 2017Date of Patent: September 4, 2018Assignee: Renesas Electronics CorporationInventors: Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
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Publication number: 20180026024Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.Type: ApplicationFiled: September 29, 2017Publication date: January 25, 2018Applicant: Renesas Electronics CorporationInventors: Takeshi OKAGAKI, Koji SHIBUTANI, Makoto YABUUCHI, Nobuhiro TSUDA
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Patent number: 9812435Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.Type: GrantFiled: August 14, 2015Date of Patent: November 7, 2017Assignee: Renesas Electronics CorporationInventors: Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
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Publication number: 20160049395Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.Type: ApplicationFiled: August 14, 2015Publication date: February 18, 2016Applicant: Renesas Electronics CorporationInventors: Takeshi OKAGAKI, Koji SHIBUTANI, Makoto YABUUCHI, Nobuhiro TSUDA
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Publication number: 20160043080Abstract: A semiconductor device is provided which suppresses variations in transistor characteristics such as a source-drain diffusion capacitance. A first transistor TRA is formed in a first element forming area EFA as a divided transistor. A second transistor TRB is formed in a second element forming area EFB as another divided transistor. The first element forming area EFA and the second element forming area EFB are set to the same size. The first element forming area EFA and the second element forming area EFB are arranged deviated from each other in an X direction by a length SPL corresponding to the minimum pitch PT of a gate wiring GH.Type: ApplicationFiled: July 24, 2015Publication date: February 11, 2016Applicant: Renesas Electronics CorporationInventors: Tetsuya WATANABE, Nobuhiro TSUDA
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Patent number: 9035392Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.Type: GrantFiled: February 20, 2014Date of Patent: May 19, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Nobuhiro Tsuda, Hidekatsu Nishimaki, Hiroshi Omura, Yuko Yoshifuku
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Publication number: 20140239406Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.Type: ApplicationFiled: February 20, 2014Publication date: August 28, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Nobuhiro TSUDA, Hidekatsu NISHIMAKI, Hiroshi OMURA, Yuko YOSHIFUKU
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Patent number: 8710552Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.Type: GrantFiled: June 29, 2012Date of Patent: April 29, 2014Assignee: Renesas Electronics CorporationInventors: Nobuhiro Tsuda, Hidekatsu Nishimaki, Hiroshi Omura, Yuko Yoshifuku
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Publication number: 20120261723Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.Type: ApplicationFiled: June 29, 2012Publication date: October 18, 2012Applicant: Renesas Electronics CorporationInventors: Nobuhiro TSUDA, Hidekatsu NISHlMAKI, Hiroshi OMURA, Yuko YOSHIFUKU
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Patent number: 8264011Abstract: CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration.Type: GrantFiled: September 29, 2011Date of Patent: September 11, 2012Assignee: Renesas Electronics CorporationInventor: Nobuhiro Tsuda
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Patent number: 8237203Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.Type: GrantFiled: August 5, 2009Date of Patent: August 7, 2012Assignee: Renesas Electronics CorporationInventors: Nobuhiro Tsuda, Hidekatsu Nishimaki, Hiroshi Omura, Yuko Yoshifuku
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Publication number: 20120018839Abstract: CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration.Type: ApplicationFiled: September 29, 2011Publication date: January 26, 2012Applicant: Renesas Electronics CorporationInventor: Nobuhiro TSUDA
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Patent number: 8063415Abstract: CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration.Type: GrantFiled: July 23, 2008Date of Patent: November 22, 2011Assignee: Renesas Electronics CorporationInventor: Nobuhiro Tsuda
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Publication number: 20100044755Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.Type: ApplicationFiled: August 5, 2009Publication date: February 25, 2010Inventors: Nobuhiro TSUDA, Hidekatsu Nishimaki, Hiroshi Omura, Yuko Yoshifuku
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Publication number: 20090026503Abstract: CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration.Type: ApplicationFiled: July 23, 2008Publication date: January 29, 2009Inventor: Nobuhiro TSUDA