Abstract: A memory device that consumes no wasteful power in selecting memory cells and achieves high operating speed and size and cost reductions, is provided. In reading of memory cell information, only a single memory cell in a single local block is activated through a read word line. Specifically, AND circuits are provided in correspondence with all memory cells. Each AND circuit receives as its inputs a block select signal for selecting one of the local blocks and an in-block memory cell select signal for selecting one of the memory cells in each local block in a common manner among the local blocks. The outputs from the AND circuits are applied to read word lines. Unselected memory cells are not activated and therefore no current flows from those memory cells to local read bit lines, thereby preventing wasteful power consumption.

Abstract: A memory device that consumes no wasteful power in selecting memory cells and achieves high operating speed and size and cost reductions, is provided. In reading of memory cell information, only a single memory cell in a single local block is activated through a read word line. Specifically, AND circuits are provided in correspondence with all memory cells. Each AND circuit receives as its inputs a block select signal for selecting one of the local blocks and an in-block memory cell select signal for selecting one of the memory cells in each local block in a common manner among the local blocks. The outputs from the AND circuits are applied to read word lines. Unselected memory cells are not activated and therefore no current flows from those memory cells to local read bit lines, thereby preventing wasteful power consumption.

Abstract: An SRAM memory cell is constituted by complementarily connecting first inverter composed of NMOS transistor and a PMOS transistor, and a second inverter composed of another NMOS transistor and another PMOS transistor. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the first inverter. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the second inverter. As a result, capacity values for gate capacities are added to the storage nodes.

Abstract: An SRAM memory cell is constituted by complementarily connecting first inverter composed of NMOS transistor and a PMOS transistor, and a second inverter composed of another NMOS transistor and another PMOS transistor. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the first inverter. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the second inverter. As a result, capacity values for gate capacities are added to the storage nodes.

Abstract: The synchronous semiconductor memory device related to the present invention is a synchronous semiconductor memory device in which for one data read signal, the respective data corresponding to a plurality of addresses are sequentially read out from a memory cell in synchronism with an external clock signal, and which comprises a control circuit which executes control according to an externally inputted control signal so as to output only the data corresponding to one address from the memory cell for one data read signal.

Abstract: The synchronous semiconductor memory device related to the present invention is a synchronous semiconductor memory device in which for one data read signal, the respective data corresponding to a plurality of addresses are sequentially read out from a memory cell in synchronism with an external clock signal, and which comprises a control circuit which executes control according to an externally inputted control signal so as to output only the data corresponding to one address from the memory cell for one data read signal.

Abstract: The synchronous semiconductor memory device related to the present invention is a synchronous semiconductor memory device in which for one data read signal, the respective data corresponding to a plurality of addresses are sequentially read out from a memory cell in synchronism with an external clock signal, and which comprises a control circuit which executes control according to an externally inputted control signal so as to output only the data corresponding to one address from the memory cell for one data read signal.

Abstract: A semiconductor memory device includes an array of memory cells arranged in rows and columns; a plurality of word lines connected to the rows of the memory cells; a plurality of bit lines connected to the columns of the memory cells; word line selection means; bit line selection means; and equalizing means for equalizing the bit line to a desired voltage level in response to an address signal, and for terminating the equalization in response to change in a signal on a word line according to change in the address signal.

Abstract: In a boron diffusion process, a multiplicity of semiconductor wafers and pyrolytic boron nitride dopant disks are placed in a diffusion tube kept in an inert atmosphere at a high temperature, and boron diffusion is performed with hydrogen injection, the initial concentration of hydrogen in the diffusion tube being a very low range of 0.05% by volume at maximum. The result is that it is possible to improve dispersion of sheet resistivity (.rho.s) of the silicon wafer surface remarkably and to suppress occurrence of lattice defects.

Abstract: A cantilever stylus suited for use in an atomic force microscope is made in the following processes: forming a first film on a substrate; forming a second film of metallic material on an external surface of the first film; forming a photoresist film on an external surface of the second film by making use of a photolithography technique; performing etching with respect to the second film with only a portion thereof covered with the photoresist film left on the first film; and further performing etching with respect to the first film with the second film being used as a resist film so that the first film may be configured into a cantilever stylus.

Abstract: A fine positioning device such as a stage device for placing a probe or a sample thereon in a scanning tunneling microscope comprises a fixed member, a first structure spring stage having a first base member integral with the fixed member, a first moving member and a first resilient member for resiliently coupling the first base member and the first moving member such that they are displaceable relative to each other in a predetermined direction, a first actuator for displacing the first moving member relative to the base member in the predetermined direction, a second structure spring stage having a second base member integral with the first moving member, a second moving member and a second resilient member for resilient coupling the second base member and the second moving member such that they are displaceable relative to each other in a direction parallel to the predetermined direction, and a second actuator for displacing the second moving member relative to the second base member in the parallel direct