Patents by Inventor Nobumichi Okazaki
Nobumichi Okazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8446756Abstract: Provided is a method of driving a storage device capable of improving reliability of data write in the storage device including a variable resistance element. At the time of data write operation, a plurality of write pulses having shapes different from each other are applied between electrodes 21 and 24 in a variable resistance element 2. Diffusion loss of a conductive path caused by self-heat generation (generation of Joule heat) of the variable resistance element 2 may be prevented, and thus data hold operation after write is stabilized. Also, the variable resistance element 2 may be prevented from being destructed when the write operation is sufficiently performed, and thus the data write operation is stabilized.Type: GrantFiled: August 12, 2008Date of Patent: May 21, 2013Assignee: Sony CorporationInventors: Tsunenori Shiimoto, Nobumichi Okazaki, Tomohito Tsushima
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Publication number: 20110026298Abstract: Provided is a method of driving a storage device capable of improving reliability of data write in the storage device including a variable resistance element. At the time of data write operation, a plurality of write pulses having shapes different from each other are applied between electrodes 21 and 24 in a variable resistance element 2. Diffusion loss of a conductive path caused by self-heat generation (generation of Joule heat) of the variable resistance element 2 may be prevented, and thus data hold operation after write is stabilized. Also, the variable resistance element 2 may be prevented from being destructed when the write operation is sufficiently performed, and thus the data write operation is stabilized.Type: ApplicationFiled: August 12, 2008Publication date: February 3, 2011Applicant: SONY CORPORATIONInventors: Tsunenori Shiimoto, Nobumichi Okazaki, Tomohito Tsushima
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Patent number: 7719873Abstract: A memory includes: memory elements arranged in a matrix, each memory element having such characteristics that when an electric signal at a level equal to or higher than that of a first threshold signal is applied to the memory element, the resistance thereof is changed from a high value to a low value, and when an electric signal at a level equal to or higher than that of a second threshold signal is applied thereto, the resistance is changed from the low value to the high value, the polarities of the first and second threshold signals being different from each other; electric circuits for applying electric signals to the memory elements; and detection units each for measuring a current flowing through the corresponding memory element or a voltage applied thereto from the start of the application of electric signals to detect whether the resistance is high or low.Type: GrantFiled: November 3, 2005Date of Patent: May 18, 2010Assignee: Sony CorporationInventors: Hidenari Hachino, Hironobu Mori, Nobumichi Okazaki, Katsuhisa Aratani
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Patent number: 7599210Abstract: One or serially connected field effect transistors are cross coupled with each other, first terminals of nonvolatile variable resistance elements are connected to their storage nodes, and the other terminals of the variable resistance elements are connected to a power supply line to thereby form a memory cell. By controlling the voltage supplied to this power supply line, data of the memory cell immediately before turning off the power is stored in it when the power is turned off.Type: GrantFiled: August 10, 2006Date of Patent: October 6, 2009Assignee: Sony CorporationInventors: Nobumichi Okazaki, Tsunenori Shiimoto, Hidenari Hachino, Wataru Otsuka
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Patent number: 7583525Abstract: A method of driving a storage device including a variable resistance element in which resistance value is changed reversibly between a high resistance state and a low resistance state by applying voltages with different polarities between two electrodes is provided. The storage device includes a plurality of memory cells formed of the variable resistance elements. The method includes the step of applying voltages more than once in combination to the memory cell when the variable resistance element is changed from the low resistance state to the high resistance state.Type: GrantFiled: April 23, 2007Date of Patent: September 1, 2009Assignee: Sony CorporationInventors: Tsunenori Shiimoto, Nobumichi Okazaki, Hironobu Mori, Tomohito Tsushima
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Patent number: 7542335Abstract: It is a task to provide a magnetic storage device of complementary type, of which reliability is improved by precisely performing writing storage data. In the present invention, therefore, in a magnetic storage device of complementary type for storing storage data contrary to each other in a first ferromagnetic tunnel junction element and a second ferromagnetic tunnel junction element, respectively, the first ferromagnetic tunnel junction element and the second ferromagnetic tunnel junction element are formed adjacently on a semiconductor substrate, first writing lines is wound around the first ferromagnetic tunnel junction element like a coil and the same time second writing lines is wound around the second ferromagnetic tunnel junction element like a coil, and in addition, a winding direction of the first writing lines and a winding direction of the second writing lines are reversed to each other.Type: GrantFiled: September 18, 2003Date of Patent: June 2, 2009Assignee: Sony CorporationInventors: Hiroshi Yoshihara, Katsutoshi Moriyama, Hironobu Mori, Nobumichi Okazaki
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Patent number: 7471543Abstract: A storage device includes a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from the first threshold voltage, and a circuit element connected in series with the storage element, wherein letting R be a resistance value of the storage element after writing, V be the second threshold voltage, and I be a current that can be passed through the storage element at a time of erasure, R?V/I.Type: GrantFiled: September 11, 2006Date of Patent: December 30, 2008Assignee: Sony CorporationInventors: Chieko Nakashima, Hidenari Hachino, Hajime Nagao, Nobumichi Okazaki
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Patent number: 7423902Abstract: A storage device includes memory cells disposed in a matrix. The memory cells each include a storage element whose resistance changes from a higher state to a lower state when an electric signal of a first threshold level or higher is applied and whose resistance changes from the lower state to the higher state when an electric signal of a second threshold level or higher whose polarity is different from the polarity of the electric signal of the first threshold level or higher is applied, and a circuit element connected in series with the storage element. In a state in which an erasing voltage is applied to at least one memory cell on which erasing is currently being performed, after the lapse of a predetermined time from the application, an erasing voltage is applied to at least one memory cell on which erasing is to be next performed.Type: GrantFiled: May 25, 2006Date of Patent: September 9, 2008Assignee: Sony CorporationInventors: Hironobu Mori, Hidenari Hachino, Nobumichi Okazaki
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Patent number: 7372718Abstract: A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.Type: GrantFiled: October 4, 2005Date of Patent: May 13, 2008Assignee: Sony CorporationInventors: Hajime Nagao, Hidenari Hachino, Tsutomu Sagara, Hironobu Mori, Nobumichi Okazaki, Wataru Ootsuka, Tomohito Tsushima, Chieko Nakashima
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Patent number: 7345908Abstract: The present invention is to provide a memory device including: a plurality of memory cells that each include a memory element having a memory layer and first and second electrodes that sandwich the memory layer, the plurality of memory cells being divided into memory blocks of m columns by n rows (m and n are each an integer of not less than 1, m+n?3), the memory elements in the same memory block having the first electrode that is formed of a single layer in common to the memory elements; and a voltage application unit that applies any voltage to the first electrode of the memory block.Type: GrantFiled: July 10, 2006Date of Patent: March 18, 2008Assignee: Sony CorporationInventors: Hidenari Hachino, Nobumichi Okazaki, Katsuhisa Aratani
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Patent number: 7336520Abstract: A storage device includes a storage element having first and second terminals that cause a first electrical characteristic change when an electric signal of a first threshold level or higher is applied and that cause a second electrical characteristic change, which is asymmetrical to the first electrical characteristic change, when an electric signal of a second threshold level or higher, the polarity of the electric signal of the second threshold level or higher being different from the polarity of the electric signal of the first threshold level or higher, is applied; and a unipolar transistor connected in series with the storage element. One of the first terminal and the second terminal of the storage element is electrically connected to the unipolar transistor. The unipolar transistor has a negative polarity or a positive polarity in accordance with the first terminal or the second terminal electrically connected to the unipolar transistor.Type: GrantFiled: June 6, 2006Date of Patent: February 26, 2008Assignee: Sony CorporationInventors: Hidenari Hachino, Nobumichi Okazaki, Katsuhisa Aratani
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Publication number: 20070247894Abstract: A method of driving a storage device including a variable resistance element in which resistance value is changed reversibly between a high resistance state and a low resistance state by applying voltages with different polarities between two electrodes is provided. The storage device includes a plurality of memory cells formed of the variable resistance elements. The method includes the step of applying voltages more than once in combination to the memory cell when the variable resistance element is changed from the low resistance state to the high resistance state.Type: ApplicationFiled: April 23, 2007Publication date: October 25, 2007Applicant: SONY CORPORATIONInventors: Tsunenori Shiimoto, Nobumichi Okazaki, Hironobu Mori, Tomohito Tsushima
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Patent number: 7242606Abstract: A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.Type: GrantFiled: September 13, 2005Date of Patent: July 10, 2007Assignee: Sony CorporationInventors: Hidenari Hachino, Nobumichi Okazaki, Wataru Otsuka, Tomohito Tsushima, Tsutomu Sagara, Chieko Nakashima, Hironobu Mori, Hajime Nagao
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Publication number: 20070153564Abstract: A storage device includes memory cells disposed in a matrix. The memory cells each include a storage element whose resistance changes from a higher state to a lower state when an electric signal of a first threshold level or higher is applied and whose resistance changes from the lower state to the higher state when an electric signal of a second threshold level or higher whose polarity is different from the polarity of the electric signal of the first threshold level or higher is applied, and a circuit element connected in series with the storage element. In a state in which an erasing voltage is applied to at least one memory cell on which erasing is currently being performed, after the lapse of a predetermined time from the application, an erasing voltage is applied to at least one memory cell on which erasing is to be next performed.Type: ApplicationFiled: May 25, 2006Publication date: July 5, 2007Inventors: Hironobu Mori, Hidenari Hachino, Nobumichi Okazaki
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Patent number: 7221600Abstract: An arithmetic circuit is provided having a compact and high-speed logic-in-memory wherein various operations are performed. The arithmetic circuit includes a memory element having a variable resistance element R in which the state of resistance changes reversibly between the state of high resistance and the state of low resistance by applying voltages with different polarities between one electrode and the other electrode, and at least one transistor of MRD, MRS, MW1 and MW2 connected respectively to both ends of the memory element; wherein data is stored in the memory element, the operation for the external data X, W, Y1 and Y2 input through any of the transistors is performed by applying potential to each of the ends of the memory element through the transistors MRD, MRS, MW1, and MW2, and a result of the operation is output from the memory element.Type: GrantFiled: July 21, 2005Date of Patent: May 22, 2007Assignee: Sony CorporationInventors: Masaaki Hara, Nobumichi Okazaki
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Patent number: 7209379Abstract: A storage device is proposed, which includes: a source line arranged along a row direction; a bit line arranged along a column direction; a storage element arranged at an intersection of the source line and the bit line; a writing circuit connected to one terminal of the bit line and applying a predetermined voltage to the bit line; and a voltage adjusting circuit connected to a storage element that is located closest to another terminal of the bit line; wherein the voltage adjusting circuit compares the voltage applied to the storage element located closest to the another terminal of the bit line with a setting voltage to thereby adjust the voltage that the writing circuit applies to the bit line.Type: GrantFiled: September 13, 2005Date of Patent: April 24, 2007Assignee: Sony CorporationInventors: Hironobu Mori, Hidenari Hachino, Chieko Nakashima, Tsutomu Sagara, Nobumichi Okazaki, Hajime Nagao
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Publication number: 20070070682Abstract: A storage device includes a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from the first threshold voltage, and a circuit element connected in series with the storage element, wherein letting R be a resistance value of the storage element after writing, V be the second threshold voltage, and I be a current that can be passed through the storage element at a time of erasure, R?V/I.Type: ApplicationFiled: September 11, 2006Publication date: March 29, 2007Inventors: Chieko Nakashima, Hidenari Hachino, Hajime Nagao, Nobumichi Okazaki
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Publication number: 20070041242Abstract: One or serially connected field effect transistors are cross coupled with each other, first terminals of nonvolatile variable resistance elements are connected to their storage nodes, and the other terminals of the variable resistance elements are connected to a power supply line to thereby form a memory cell. By controlling the voltage supplied to this power supply line, data of the memory cell immediately before turning off the power is stored in it when the power is turned off.Type: ApplicationFiled: August 10, 2006Publication date: February 22, 2007Applicant: Sony CorporationInventors: Nobumichi Okazaki, Tsunenori Shiimoto, Hidenari Hachino, Wataru Otsuka
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Publication number: 20070012959Abstract: The present invention is to provide a memory device including: a plurality of memory cells that each include a memory element having a memory layer and first and second electrodes that sandwich the memory layer, the plurality of memory cells being divided into memory blocks of m columns by n rows (m and n are each an integer of not less than 1, m+n?3), the memory elements in the same memory block having the first electrode that is formed of a single layer in common to the memory elements; and a voltage application unit that applies any voltage to the first electrode of the memory block.Type: ApplicationFiled: July 10, 2006Publication date: January 18, 2007Inventors: Hidenari Hachino, Nobumichi Okazaki, Katsuhisa Aratani
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Publication number: 20060279983Abstract: A storage device includes a storage element having first and second terminals that cause a first electrical characteristic change when an electric signal of a first threshold level or higher is applied and that cause a second electrical characteristic change, which is asymmetrical to the first electrical characteristic change, when an electric signal of a second threshold level or higher, the polarity of the electric signal of the second threshold level or higher being different from the polarity of the electric signal of the first threshold level or higher, is applied; and a unipolar transistor connected in series with the storage element. One of the first terminal and the second terminal of the storage element is electrically connected to the unipolar transistor. The unipolar transistor has a negative polarity or a positive polarity in accordance with the first terminal or the second terminal electrically connected to the unipolar transistor.Type: ApplicationFiled: June 6, 2006Publication date: December 14, 2006Inventors: Hidenari Hachino, Nobumichi Okazaki, Katsuhisa Aratani