Patents by Inventor Nobumichi Okazaki

Nobumichi Okazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7130224
    Abstract: An object of the present invention is to provide a compound storage circuit that includes a storage circuit including a volatile storage circuit and a nonvolatile storage circuit connected in parallel to each other and that is arranged to be capable of an instant-on function by storing information equal to storage information stored in the volatile storage circuit into the nonvolatile storage circuit, the compound storage circuit being capable of reducing power consumption, and a semiconductor device including the compound storage circuit.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: October 31, 2006
    Assignee: Sony Corporation
    Inventors: Katsutoshi Moriyama, Hironobu Mori, Nobumichi Okazaki
  • Publication number: 20060109316
    Abstract: A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.
    Type: Application
    Filed: October 4, 2005
    Publication date: May 25, 2006
    Inventors: Hajime Nagao, Hidenari Hachino, Tsutomu Sagara, Hironobu Mori, Nobumichi Okazaki, Wataru Ootsuka, Tomohito Tsushima, Chieko Nakashima
  • Publication number: 20060092737
    Abstract: A memory includes: memory elements arranged in a matrix, each memory element having such characteristics that when an electric signal at a level equal to or higher than that of a first threshold signal is applied to the memory element, the resistance thereof is changed from a high value to a low value, and when an electric signal at a level equal to or higher than that of a second threshold signal is applied thereto, the resistance is changed from the low value to the high value, the polarities of the first and second threshold signals being different from each other; electric circuits for applying electric signals to the memory elements; and detection units each for measuring a current flowing through the corresponding memory element or a voltage applied thereto from the start of the application of electric signals to detect whether the resistance is high or low.
    Type: Application
    Filed: November 3, 2005
    Publication date: May 4, 2006
    Inventors: Hidenari Hachino, Hironobu Mori, Nobumichi Okazaki, Katsuhisa Aratani
  • Publication number: 20060067114
    Abstract: A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 30, 2006
    Inventors: Hidenari Hachino, Nobumichi Okazaki, Wataru Otsuka, Tomohito Tsushima, Tsutomu Sagara, Chieko Nakashima, Hironobu Mori, Hajime Nagao
  • Publication number: 20060067106
    Abstract: A storage device is proposed, which includes: a source line arranged along a row direction; a bit line arranged along a column direction; a storage element arranged at an intersection of the source line and the bit line; a writing circuit connected to one terminal of the bit line and applying a predetermined voltage to the bit line; and a voltage adjusting circuit connected to a storage element that is located closest to another terminal of the bit line; wherein the voltage adjusting circuit compares the voltage applied to the storage element located closest to the another terminal of the bit line with a setting voltage to thereby adjust the voltage that the writing circuit applies to the bit line.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 30, 2006
    Inventors: Hironobu Mori, Hidenari Hachino, Chieko Nakashima, Tsutomu Sagara, Nobumichi Okazaki, Hajime Nagao
  • Patent number: 7020010
    Abstract: A magnetic storage apparatus provided using ferromagnetic tunnel junction devices is constituted by forming the ferromagnetic tunnel junction device by laminating a fixed magnetization layer and a free magnetization layer on top and back surfaces of a tunnel barrier layer, respectively, wiring word lines in the magnetization direction of the fixed magnetization layer of the ferromagnetic tunnel junction device, and wiring bit lines in the direction orthogonal to the magnetization direction of the fixed magnetization layer of the ferromagnetic tunnel junction device, wherein two different memory states can be written in the ferromagnetic tunnel junction device by inverting the direction of the current flowing through the bit lines. At the time of writing in the ferromagnetic tunnel junction device, the direction of the current flowing through the word line is inverted in the same direction as or the opposite direction to the magnetization direction of the fixed magnetization layer.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: March 28, 2006
    Assignee: Sony Corporation
    Inventors: Katsutoshi Moriyama, Hironobu Mori, Nobumichi Okazaki
  • Publication number: 20060028247
    Abstract: An arithmetic circuit having a high versatility, with which such a circuit as a compact and high-speed logic-in-memory is obtained and various operations is performed, is provided. The arithmetic circuit includes a memory element having a variable resistance element R in which the state of resistance changes reversibly between the state of high resistance and the state of low resistance by applying voltages with different polarities between one electrode and the other electrode, and at least one transistor of MRD, MRS, MW1 and MW2 connected respectively to both ends of the memory element; wherein data is stored in the memory element, the operation for the external data X, W, Y1 and Y2 input through any of the transistors is performed by applying potential to each of the ends of the memory element through the transistors MRD, MRS, MW1, and MW2, and a result of the operation is output from the memory element.
    Type: Application
    Filed: July 21, 2005
    Publication date: February 9, 2006
    Applicant: Sony Corporation
    Inventors: Masaaki Hara, Nobumichi Okazaki
  • Publication number: 20050285093
    Abstract: It is a task to provide a magnetic storage device of complementary type, of which reliability is improved by precisely performing writing storage data. In the present invention, therefore, in a magnetic storage device of complementary type for storing storage data contrary to each other in a first ferromagnetic tunnel junction element and a second ferromagnetic tunnel junction element, respectively, the first ferromagnetic tunnel junction element and the second ferromagnetic tunnel junction element are formed adjacently on a semiconductor substrate, first writing lines is wound around the first ferromagnetic tunnel junction element like a coil and the same time second writing lines is wound around the second ferromagnetic tunnel junction element like a coil, and in addition, a winding direction of the first writing lines and a winding direction of the second writing lines are reversed to each other.
    Type: Application
    Filed: September 18, 2003
    Publication date: December 29, 2005
    Inventors: Hiroshi Yoshihara, Katsutoshi Moriyama, Hironobu Mori, Nobumichi Okazaki
  • Publication number: 20050226033
    Abstract: An object of the present invention is to provide a compound storage circuit that includes a storage circuit including a volatile storage circuit and a nonvolatile storage circuit connected in parallel to each other and that is arranged to be capable of an instant-on function by storing information equal to storage information stored in the volatile storage circuit into the nonvolatile storage circuit, the compound storage circuit being capable of reducing power consumption, and a semiconductor device including the compound storage circuit.
    Type: Application
    Filed: July 22, 2003
    Publication date: October 13, 2005
    Applicant: Sony Corporation
    Inventors: Katsutoshi Moriyama, Hironobu Mori, Nobumichi Okazaki
  • Publication number: 20050105347
    Abstract: A magnetic storage apparatus provided using ferromagnetic tunnel junction devices is constituted by forming the ferromagnetic tunnel junction device by laminating a fixed magnetization layer and a free magnetization layer on top and back surfaces of a tunnel barrier layer, respectively, wiring word lines in the magnetization direction of the fixed magnetization layer of the ferromagnetic tunnel junction device, and wiring bit lines in the direction orthogonal to the magnetization direction of the fixed magnetization layer of the ferromagnetic tunnel junction device, wherein two different memory states can be written in the ferromagnetic tunnel junction device by inverting the direction of the current flowing through the bit lines. At the time of writing in the ferromagnetic tunnel junction device, the direction of the current flowing through the word line is inverted in the same direction as or the opposite direction to the magnetization direction of the fixed magnetization layer.
    Type: Application
    Filed: February 7, 2003
    Publication date: May 19, 2005
    Applicant: Sony Corporation
    Inventors: Katsutoshi Moriyama, Hironoeu Mori, Nobumichi Okazaki
  • Patent number: 4827454
    Abstract: A semiconductor memory device, which can be maintained free from malfunction despite generation of current noise due to output signal variation in a output buffer circuit, is equipped with a switch in the input stage of the output buffer circuit, and the switch is so controlled as to be turned off during the period of time in which there exists the possibility that the output signal of the output buffer circuit may be changed by an address variation resulting from any current noise generated by variation in the output signal of the output buffer circuit.
    Type: Grant
    Filed: August 27, 1987
    Date of Patent: May 2, 1989
    Assignee: Sony Corporation
    Inventor: Nobumichi Okazaki