Abstract: A doped electrode is manufactured by an electrode manufacturing method. The doped electrode includes an active material doped with an alkali metal. In the electrode manufacturing method, a dope solution is brought into contact with an electrode. The electrode includes a current collector and an active material layer. The active material layer is formed on a surface of the current collector and includes the active material. The dope solution includes an alkali metal ion and flows. In the electrode manufacturing method, for example, the alkali metal is electrically doped to the active material using a counter electrode member arranged to face the electrode.

Abstract: Apparatuses and methods for reducing standby current in memory array access circuits are disclosed. An example apparatus includes a activation voltage supply line and a sense amplifier coupled to the activation voltage supply line. The sense amplifier is configured to be activated by an activation voltage provided on the activation voltage supply line. A read-write circuit is coupled to a pair of local input/output lines and a pair of global input/output lines, and further coupled to the activation voltage supply line. The read-write circuit is configured to drive the pair global input/output lines based on voltages of the pair of local input/output lines when activated for a read operation and further configured to drive the pair of local input/output lines based on voltages of the pair of global input/output lines when activated for a write operation.

Abstract: A degradation degree assessment device for a secondary battery is to assess a degree of degradation of a secondary battery and includes a battery characteristic acquisition unit, a capacity estimation unit, and an assessment unit. The battery characteristic acquisition unit acquires a battery characteristic relating to a voltage transition of the secondary battery in a predetermined voltage section. The assessment unit assesses the degree of degradation of the secondary battery based on the battery characteristic acquired by the battery characteristic acquisition unit or based on a battery characteristic-related value computed on the basis of the battery characteristic.

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

Abstract: In a deterioration degree determination device for a secondary battery, a battery information acquisition unit acquires battery information related to the secondary battery, and a feasibility determination unit determines feasibility of determination of deterioration degree for each secondary battery based on the battery information and a feasibility determination reference prepared in advance. A battery characteristic acquisition unit acquires a battery characteristic related to transition of a battery state in a predetermined voltage section for the secondary battery for which the determination of the deterioration degree is determined to be feasible by the feasibility determination unit.

Abstract: A deterioration degree determination device includes a charging and discharging control unit, a battery characteristic acquisition unit, and a determination unit. The charging and discharging control unit, in a state where multiple secondary batteries are connected to each other to form a battery pack, performs a charging and discharging operation of the battery pack while voltages of the secondary batteries are individually measured. The battery characteristic acquisition unit acquires a battery characteristic related to transition in a battery state over a predetermined voltage section for at least some of the multiple secondary batteries. The determination unit determines a deterioration degree of at least some of the multiple secondary batteries based on the battery characteristic or a battery characteristic relationship value calculated based on the battery characteristic.

Abstract: A server for a deterioration degree determination system for a secondary battery includes an estimation formula memory unit and an update unit. The estimation formula memory unit stores an estimation formula for determining a deterioration degree based on a battery characteristic related to transition of a battery state over a predetermined voltage section in the secondary battery or a battery characteristic relationship value related to the battery characteristic. The update unit that updates the estimation formula stored in the estimation formula memory unit based on the battery characteristic related to the transition of the battery state of the secondary battery acquired by charging and discharging the secondary battery in an external terminal.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for a sequence of refreshing memory mats. During a refresh operation, wordlines of the memory may be refreshed in a sequence. Groups of wordlines may be organized into memory mats. In order to prevent noise, each time a wordline in a memory mat is refreshed, the next wordline to be refreshed may be in a mat which is not physically adjacent to the mat containing the previously refreshed wordline.

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

Abstract: A battery monitoring system includes a data acquiring unit and a failure determining unit. The data acquiring unit acquires a plurality of types of monitoring data to monitor a state of a secondary battery. The failure determining unit determines whether the secondary battery has failed. The failure determining unit performs sparsity regularization using the monitoring data as variables and calculates a partial correlation coefficient matrix of the monitoring data. The failure determining unit calculates, as an abnormality level, an amount of change in a partial correlation coefficient, which is a component of the partial correlation coefficient matrix, between two partial correlation coefficient matrices calculated at different periods. The failure determining unit determines that the secondary battery has failed when the calculated abnormality level exceeds a predetermined threshold.

Abstract: A used secondary battery module management system server manages a manufacture of a battery assembly. The server stores, in a memory, a correspondence relationship of each of secondary battery modules among identification information, ranks, and status information. The server extracts an available rank from the ranks in response to a rebuilding request for the battery assembly. The available rank is a rank in which the number of the secondary battery modules having the status information indicating that the secondary battery modules are available is equal to or larger than the number of the secondary battery modules required to constitute the battery assembly. The server receives, from an external terminal, the identification information on each of selection secondary battery modules having an identical rank.

Abstract: Methods, systems, and devices for reading and writing memory management data using a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

Abstract: A used secondary battery module management system server manages a manufacture of a battery assembly. The server stores, in a memory, a correspondence relationship of each of secondary battery modules among identification information, ranks, and status information. The server extracts an available rank from the ranks in response to a rebuilding request for the battery assembly. The available rank is a rank in which the number of the secondary battery modules having the status information indicating that the secondary battery modules are available is equal to or larger than the number of the secondary battery modules required to constitute the battery assembly. The server receives, from an external terminal, the identification information on each of selection secondary battery modules having an identical rank.

Abstract: An abnormality determination device for a secondary battery includes an internal-resistance calculation unit, a threshold memory unit, a capacity balance comparison unit, and an abnormality determination unit. The internal-resistance calculation unit detects an internal resistance in a negative-electrode reaction resistance dominant region in which a reaction resistance of a negative electrode is dominant in a charge and discharge reaction of the secondary battery. The threshold memory unit stores a capacity balance threshold used as a reference for determining abnormality in a balance between a capacity of a positive electrode and a capacity of the negative electrode in the secondary battery. The capacity balance comparison unit compares the internal resistance calculated by the internal-resistance calculation unit with the capacity balance threshold stored in the threshold memory unit.

Abstract: A degradation degree assessment device for a secondary battery is to assess a degree of degradation of a secondary battery and includes a battery characteristic acquisition unit, a capacity estimation unit, and an assessment unit. The battery characteristic acquisition unit acquires a battery characteristic relating to a voltage transition of the secondary battery in a predetermined voltage section. The assessment unit assesses the degree of degradation of the secondary battery based on the battery characteristic acquired by the battery characteristic acquisition unit or based on a battery characteristic-related value computed on the basis of the battery characteristic.

Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

Abstract: Apparatuses and methods for controlling driving signals are disclosed herein. Word drivers may be included in a memory device for driving hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. In driving the word lines, driving signals are driven between an active state having an active voltage and an inactive state having an inactive voltage. The active voltage may be a voltage of a power supply and the inactive voltage may be an intermediate voltage between the active voltage and a reference voltage, such as ground. Driving the driving signals in such a manner may reduce current consumption of the memory device in some operations, for example, such as refresh operations.

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.