Patents by Inventor Nobuo Yamamoto

Nobuo Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220229120
    Abstract: A used secondary battery module management system server manages a manufacture of a battery assembly. The server stores, in a memory, a correspondence relationship of each of secondary battery modules among identification information, ranks, and status information. The server extracts an available rank from the ranks in response to a rebuilding request for the battery assembly. The available rank is a rank in which the number of the secondary battery modules having the status information indicating that the secondary battery modules are available is equal to or larger than the number of the secondary battery modules required to constitute the battery assembly. The server receives, from an external terminal, the identification information on each of selection secondary battery modules having an identical rank.
    Type: Application
    Filed: January 17, 2022
    Publication date: July 21, 2022
    Inventors: Keisuke GOTO, Haruki TANAKA, Mayu IIDA, Hiroyasu SUZUKI, Nobuo YAMAMOTO, Shogo SUZUKI
  • Patent number: 11340277
    Abstract: An abnormality determination device for a secondary battery includes an internal-resistance calculation unit, a threshold memory unit, a capacity balance comparison unit, and an abnormality determination unit. The internal-resistance calculation unit detects an internal resistance in a negative-electrode reaction resistance dominant region in which a reaction resistance of a negative electrode is dominant in a charge and discharge reaction of the secondary battery. The threshold memory unit stores a capacity balance threshold used as a reference for determining abnormality in a balance between a capacity of a positive electrode and a capacity of the negative electrode in the secondary battery. The capacity balance comparison unit compares the internal resistance calculated by the internal-resistance calculation unit with the capacity balance threshold stored in the threshold memory unit.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: May 24, 2022
    Assignee: DENSO CORPORATION
    Inventors: Nobuo Yamamoto, Ichiro Yamada, Shuhei Yoshida, Masaya Nakamura, Takehiko Yamaki, Hiroyasu Suzuki, Katsuki Hayashi
  • Publication number: 20220146590
    Abstract: A degradation degree assessment device for a secondary battery is to assess a degree of degradation of a secondary battery and includes a battery characteristic acquisition unit, a capacity estimation unit, and an assessment unit. The battery characteristic acquisition unit acquires a battery characteristic relating to a voltage transition of the secondary battery in a predetermined voltage section. The assessment unit assesses the degree of degradation of the secondary battery based on the battery characteristic acquired by the battery characteristic acquisition unit or based on a battery characteristic-related value computed on the basis of the battery characteristic.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 12, 2022
    Applicant: DENSO CORPORATION
    Inventors: Tomomi ASAI, Nobuo YAMAMOTO, Hiroyasu SUZUKI, Katsuki HAYASHI, Yuya MINABE
  • Patent number: 11322218
    Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nobuo Yamamoto, Donald Martin Morgan, Victor Wong, Jongtae Kwak
  • Patent number: 11302382
    Abstract: Apparatuses and methods for controlling driving signals are disclosed herein. Word drivers may be included in a memory device for driving hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. In driving the word lines, driving signals are driven between an active state having an active voltage and an inactive state having an inactive voltage. The active voltage may be a voltage of a power supply and the inactive voltage may be an intermediate voltage between the active voltage and a reference voltage, such as ground. Driving the driving signals in such a manner may reduce current consumption of the memory device in some operations, for example, such as refresh operations.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Takamasa Suzuki, Nobuo Yamamoto
  • Publication number: 20210407556
    Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventors: Yasushi Matsubara, Yusuke Jono, Donald Martin Morgan, Nobuo Yamamoto
  • Publication number: 20210383888
    Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 9, 2021
    Inventors: Nobuo Yamamoto, Donald Martin Morgan, Victor Wong, Jongtae Kwak
  • Publication number: 20210339653
    Abstract: In a system for setting power supply of reusable secondary cell modules, a degradation level estimation unit estimates a degradation level of a cell-module performance of each of a plurality of secondary cell modules, based on: the history information items about the respective the secondary cell modules acquired by a history information collection unit; and the cell-module performances of the respective secondary cell modules collected by a cell performance collection unit. A suppliable quantity prediction unit predicts a suppliable quantity of power of each of the plurality of secondary cell modules in accordance with the degradation level of the cell-module performance of a corresponding one of the plurality of secondary cell modules. A supply balance setting unit sets a power supply balance among the plurality of secondary cell modules based on the suppliable quantity of power of each of the plurality of secondary cell modules predicted by the prediction unit.
    Type: Application
    Filed: July 16, 2021
    Publication date: November 4, 2021
    Applicant: DENSO CORPORATION
    Inventors: Nobuo YAMAMOTO, Shuhei YOSHIDA, Katsuki HAYASHI, Takehiko YAMAKI, Hiroyasu SUZUKI, Yuya MINABE
  • Patent number: 11150309
    Abstract: An apparatus for estimating a degradation degree of a secondary battery includes a pulse current applying unit that applies a pulse current; a voltage acquiring unit that acquires a charge voltage and a discharge voltage which are produced at the secondary battery by applying the pulse current; a relative value calculation unit that calculates a relative value between the charge voltage and the discharge voltage; a correlation storage unit that stores a correlation between a relative value between the charge voltage and the discharge voltage, and a degradation degree of the secondary battery; and a degradation degree estimation unit that obtains a degradation degree of the secondary battery from the correlation storage unit, based on the relative value calculated by the relative value calculation unit.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: October 19, 2021
    Assignee: DENSO CORPORATION
    Inventors: Yoshinori Sato, Shuhei Yoshida, Nobuo Yamamoto, Yuta Shimonishi
  • Publication number: 20210183429
    Abstract: Apparatuses and methods for controlling driving signals are disclosed herein. Word drivers may be included in a memory device for driving hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. In driving the word lines, driving signals are driven between an active state having an active voltage and an inactive state having an inactive voltage. The active voltage may be a voltage of a power supply and the inactive voltage may be an intermediate voltage between the active voltage and a reference voltage, such as ground. Driving the driving signals in such a manner may reduce current consumption of the memory device in some operations, for example, such as refresh operations.
    Type: Application
    Filed: February 25, 2021
    Publication date: June 17, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Takamasa Suzuki, Nobuo Yamamoto
  • Patent number: 10950294
    Abstract: Apparatuses and methods for controlling driving signals are disclosed herein. Word drivers may be included in a memory device for driving hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. In driving the word lines, driving signals are driven between an active state having an active voltage and an inactive state having an inactive voltage. The active voltage may be a voltage of a power supply and the inactive voltage may be an intermediate voltage between the active voltage and a reference voltage, such as ground. Driving the driving signals in such a manner may reduce current consumption of the memory device in some operations, for example, such as refresh operations.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Takamasa Suzuki, Nobuo Yamamoto
  • Publication number: 20200371145
    Abstract: An abnormality determination device for a secondary battery includes an internal-resistance calculation unit, a threshold memory unit, a capacity balance comparison unit, and an abnormality determination unit. The internal-resistance calculation unit detects an internal resistance in a negative-electrode reaction resistance dominant region in which a reaction resistance of a negative electrode is dominant in a charge and discharge reaction of the secondary battery. The threshold memory unit stores a capacity balance threshold used as a reference for determining abnormality in a balance between a capacity of a positive electrode and a capacity of the negative electrode in the secondary battery. The capacity balance comparison unit compares the internal resistance calculated by the internal-resistance calculation unit with the capacity balance threshold stored in the threshold memory unit.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Applicant: DENSO CORPORATION
    Inventors: Nobuo YAMAMOTO, Ichiro YAMADA, Shuhei YOSHIDA, Masaya NAKAMURA, Takehiko YAMAKI, Hiroyasu SUZUKI, Katsuki HAYASHI
  • Patent number: 10847207
    Abstract: Apparatuses and methods for maintaining an active state of a word driver signal are described. The word driver may be included in a memory device including a hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. During an operation such as a refresh operation, a driving signal provided by a word driver to a subword driver may be held in an active state while the driving signal provided by a main word driver to the subword driver transitions between active and inactive states. In some examples, the word driver may include a latch for latching an activation signal at an initiation of a refresh operation to maintain a state of the driving signal.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Nobuo Yamamoto, Takamasa Suzuki
  • Publication number: 20200342929
    Abstract: Apparatuses and methods for controlling driving signals are disclosed herein. Word drivers may be included in a memory device for driving hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. In driving the word lines, driving signals are driven between an active state having an active voltage and an inactive state having an inactive voltage. The active voltage may be a voltage of a power supply and the inactive voltage may be an intermediate voltage between the active voltage and a reference voltage, such as ground. Driving the driving signals in such a manner may reduce current consumption of the memory device in some operations, for example, such as refresh operations.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 29, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Takamasa Suzuki, Nobuo Yamamoto
  • Publication number: 20200321045
    Abstract: Apparatuses and methods for maintaining an active state of a word driver signal are described. The word driver may be included in a memory device including a hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. During an operation such as a refresh operation, a driving signal provided by a word driver to a subword driver may be held in an active state while the driving signal provided by a main word driver to the subword driver transitions between active and inactive states. In some examples, the word driver may include a latch for latching an activation signal at an initiation of a refresh operation to maintain a state of the driving signal.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 8, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Nobuo Yamamoto, Takamasa Suzuki
  • Publication number: 20200273517
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for a sequence of refreshing memory mats. During a refresh operation, wordlines of the memory may be refreshed in a sequence. Groups of wordlines may be organized into memory mats. In order to prevent noise, each time a wordline in a memory mat is refreshed, the next wordline to be refreshed may be in a mat which is not physically adjacent to the mat containing the previously refreshed wordline.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 27, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Nobuo Yamamoto
  • Patent number: 10661668
    Abstract: A power conversion apparatus capable of cheaply securing safety and achieving watertightness. The power conversion apparatus (100) has: a charging device (14) for charging from an external power source (20) to a cell (30); an inverter (13) for converting the current of the cell (30) from direct current to alternating current and supplying the current to a motor (40); and a junction box (15) for relaying an electrical connection. The inverter (13), the charging device (14), and the junction box (15) are contained in a single housing. Also, the charging device (14) and the junction box (15) are electrically connected, and the junction box (15) and the inverter (13) are electrically connected. Also, the junction box (15) and the inverter (13) are connected by a bus bar (16).
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: May 26, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Ryota Hosaka, Kazushige Kakutani, Kenji Taguchi, Takashi Kamiya, Nobuo Yamamoto
  • Publication number: 20200041576
    Abstract: An apparatus for estimating a degradation degree of a secondary battery includes a pulse current applying unit that applies a pulse current; a voltage acquiring unit that acquires a charge voltage and a discharge voltage which are produced at the secondary battery by applying the pulse current; a relative value calculation unit that calculates a relative value between the charge voltage and the discharge voltage; a correlation storage unit that stores a correlation between a relative value between the charge voltage and the discharge voltage, and a degradation degree of the secondary battery; and a degradation degree estimation unit that obtains a degradation degree of the secondary battery from the correlation storage unit, based on the relative value calculated by the relative value calculation unit.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 6, 2020
    Applicant: DENSO CORPORATION
    Inventors: Yoshinori SATO, Shuhei YOSHIDA, Nobuo YAMAMOTO, Yuta SHIMONISHI
  • Patent number: 10522817
    Abstract: A positive electrode material includes: Li2Ni?M1?M2?Mn?O4-?. ? satisfies a relational expression of 0.50<??1.33. ? satisfies a relational expression of 0.33???1.1. ? satisfies a relational expression of 0???1.00. ? satisfies a relational expression of 0??<0.67. ? satisfies a relational expression of 0???1.00. M1 is at least one type selected from Co and Ga. M2 is at least one type selected from Ge, Sn, and Sb. Li2Ni?M1?M2?Mn?O4-? has a layered structure which includes a Li layer and a Ni layer. A crystal structure of Li2Ni?M1?M2?Mn?O4-? is a superlattice structure.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: December 31, 2019
    Assignee: DENSO CORPORATION
    Inventors: Yuki Tachibana, Yoshinori Satou, Nobuo Yamamoto, Shigeki Komine, Yuta Shimonishi
  • Publication number: 20190265309
    Abstract: A battery monitoring system monitors states of at least two secondary batteries. In the system, a data acquiring unit acquires a plurality of types of monitoring data to monitor the state of each of the secondary batteries. A failure determining unit determines whether the secondary battery has failed. The failure determining unit performs sparsity regularization using the acquired monitoring data of each of the secondary batteries as variables and calculates a partial correlation coefficient matrix of the monitoring data. The failure determining unit calculates, as an abnormality level, a difference in a partial correlation coefficient, which is a component of the partial correlation coefficient matrix, between two partial correlation coefficient matrices respectively calculated using the monitoring data of the two secondary batteries. The failure determining unit determines that either of the two secondary batteries has failed when the calculated abnormality level exceeds a predetermined threshold.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 29, 2019
    Applicant: DENSO CORPORATION
    Inventors: Ichiro YAMADA, Nobuo YAMAMOTO, Shuhei YOSHIDA