Patents by Inventor Nobuto Managaki
Nobuto Managaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9698482Abstract: An antenna device of the present embodiment includes: a first conductive layer connected to a ground potential, a semiconductor device provided above the first conductive layer, a second conductive layer provided above the semiconductor device, a first via connecting the second conductive layer and the first conductive layer, a third conductive layer provided above the second conductive layer, a second via passing through the first opening, and an antenna provided above the third conductive layer. A dielectric is provided between the second conductive layer and the semiconductor device, between the third conductive layer and the second conductive layer, and between the antenna and the third conductive layer. The second conductive layer includes a first opening. The second via connects the third conductive layer and the first conductive layer.Type: GrantFiled: July 16, 2014Date of Patent: July 4, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tadahiro Sasaki, Kazuhiko Itaya, Hiroshi Yamada, Yutaka Onozuka, Nobuto Managaki, Atsuko Iida
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Publication number: 20170148713Abstract: A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.Type: ApplicationFiled: December 5, 2016Publication date: May 25, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuko IIDA, Tadahiro Sasaki, Nobuto Managaki, Yutaka Onozuka, Hiroshi Yamada
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Patent number: 9576925Abstract: A semiconductor device includes a first conductive portion, a second conductive portion, a first layer, and a second layer. The first conductive portion includes a first end portion and a first extending portion. The first extending portion extends in a first direction. The length of the first extending portion in a second direction is shorter than a length of at least a part of the first end portion in the second direction. The first layer includes multiple semiconductor chips, multiple passive chip components, and a resin. The first extending portion includes a first portion and a second portion. The first layer is provided around the first portion. The first layer expands along a first plane. The first plane intersects the first direction. The second layer includes a first multilayer wiring. The second layer expands along a second plane intersecting the first direction.Type: GrantFiled: September 30, 2015Date of Patent: February 21, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Nobuto Managaki, Hiroshi Yamada
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Patent number: 9548279Abstract: A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.Type: GrantFiled: August 22, 2014Date of Patent: January 17, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Iida, Tadahiro Sasaki, Nobuto Managaki, Yutaka Onozuka, Hiroshi Yamada
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Patent number: 9502367Abstract: A semiconductor device according to an embodiment includes a semiconductor chip, a cap disposed to face the semiconductor chip, and having a through-hole electrode arranged in a through hole, and a bump electrode provided between the semiconductor chip and the cap, wherein the bump electrode is in a protruding shape connecting the semiconductor chip and the through-hole electrode, and wherein at least a portion of the bump electrode is included in the through-hole electrode, and electrically connected thereto, so that the adhesive performance between the cap and the bump electrode can be increased.Type: GrantFiled: March 9, 2015Date of Patent: November 22, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Yutaka Onozuka, Hiroshi Yamada, Nobuto Managaki, Tadahiro Sasaki
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Publication number: 20160218076Abstract: According to one embodiment, a semiconductor device includes a first conductive portion, a second conductive portion, a first layer, and a second layer. The first conductive portion includes a first end portion and a first extending portion. The first extending portion extends in a first direction. The length of the first extending portion in a second direction is shorter than a length of at least a part of the first end portion in the second direction. The first layer includes multiple semiconductor chips, multiple passive chip components, and a resin. The first extending portion includes a first portion and a second portion. The first layer is provided around the first portion. The first layer expands along a first plane. The first plane intersects the first direction. The second layer includes a first multilayer wiring. The second layer expands along a second plane intersecting the first direction.Type: ApplicationFiled: September 30, 2015Publication date: July 28, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Nobuto MANAGAKI, Hiroshi YAMADA
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Patent number: 9397057Abstract: According to an embodiment, a semiconductor device comprises an insulative resin, an interconnect, a plurality of semiconductor elements, a first conductive unit, a first connector, and a first metal layer. The insulative resin includes a first region and a second region. At least a portion of the interconnect is arranged with at least a portion of the first region in a first direction. The first conductive unit pierces the second region in the first direction. At least a portion of the first connector is arranged with at least a portion of the first conductive unit in the first direction. At least a portion of the first connector is arranged with at least a portion of the interconnect in a second direction intersecting the first direction. The first metal layer is provided between the first conductive unit and the first connector. The first metal layer contacts the insulative resin.Type: GrantFiled: May 28, 2015Date of Patent: July 19, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Yutaka Onozuka, Hiroshi Yamada, Nobuto Managaki
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Publication number: 20150348937Abstract: According to one embodiment, a semiconductor device includes an insulative resin, an interconnect, a plurality of semiconductor elements, and a first metal member. The insulative resin includes a first region and a second region. The interconnect is arranged with the first region in a first direction. The first direction intersects a direction from the first region toward the second region. The plurality of semiconductor elements is provided between the first region and the interconnect. At least one of the plurality of semiconductor elements is electrically connected to the interconnect. The first metal member includes a first through-portion and a first end portion. The first through-portion pierces the second region in the first direction. The first end portion is connected to the first through-portion. A width of the first end portion is wider than a width of the first through-portion in a second direction intersecting the first direction.Type: ApplicationFiled: April 21, 2015Publication date: December 3, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yutaka ONOZUKA, Hiroshi YAMADA, Nobuto MANAGAKI
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Publication number: 20150348924Abstract: According to an embodiment, a semiconductor device comprises an insulative resin, an interconnect, a plurality of semiconductor elements, a first conductive unit, a first connector, and a first metal layer. The insulative resin includes a first region and a second region. At least a portion of the interconnect is arranged with at least a portion of the first region in a first direction. The first conductive unit pierces the second region in the first direction. At least a portion of the first connector is arranged with at least a portion of the first conductive unit in the first direction. At least a portion of the first connector is arranged with at least a portion of the interconnect in a second direction intersecting the first direction. The first metal layer is provided between the first conductive unit and the first connector. The first metal layer contacts the insulative resin.Type: ApplicationFiled: May 28, 2015Publication date: December 3, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yutaka Onozuka, Hiroshi Yamada, Nobuto Managaki
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Publication number: 20150279802Abstract: A semiconductor device according to an embodiment includes a semiconductor chip, a cap disposed to face the semiconductor chip, and having a through-hole electrode arranged in a through hole, and a bump electrode provided between the semiconductor chip and the cap, wherein the bump electrode is in a protruding shape connecting the semiconductor chip and the through-hole electrode, and wherein at least a portion of the bump electrode is included in the through-hole electrode, and electrically connected thereto, so that the adhesive performance between the cap and the bump electrode can be increased.Type: ApplicationFiled: March 9, 2015Publication date: October 1, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yutaka ONOZUKA, Hiroshi Yamada, Nobuto Managaki, Tadahiro Sasaki
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Publication number: 20150201488Abstract: A wiring board of an embodiment includes a through via, a first insulating film disposed around the through via, a second insulating film disposed around the first insulating film, a third insulating film disposed around the second insulating film and a resin disposed around the third insulating film. The resin includes fillers. The second insulating film has a relative permittivity lower than a relative permittivity of the first insulating film. The third insulating film has a relative permittivity higher than a relative permittivity of the second insulating film.Type: ApplicationFiled: December 30, 2014Publication date: July 16, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Nobuto MANAGAKI, Tadahiro SASAKI, Atsuko IIDA, Yutaka ONOZUKA, Hiroshi YAMADA
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Publication number: 20150084208Abstract: A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.Type: ApplicationFiled: August 22, 2014Publication date: March 26, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Atsuko IIDA, Tadahiro Sasaki, Nobuto Managaki, Yutaka Onozuka, Hiroshi Yamada
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Publication number: 20150021748Abstract: A semiconductor device of an embodiment includes: a substrate, a high-frequency integrated circuit being provided on the substrate, a cap, and a sealing wall provided between the substrate and the cap. The cap includes a first conductive layer, a second conductive layer, an insulating layer provided between the first conductive layer and the second conductive layer, and a conductive via provided in the insulating layer. The conductive via connects the first conductive layer and the second conductive layer. The first conductive layer or the second conductive layer is connected to a ground potential. The sealing wall surrounds the high-frequency integrated circuit.Type: ApplicationFiled: July 16, 2014Publication date: January 22, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Tadahiro SASAKI, Kazuhiko Itaya, Hiroshi Yamada, Yutaka Onozuka, Nobuto Managaki
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Publication number: 20150022416Abstract: An antenna device of the present embodiment includes: a first conductive layer connected to a ground potential, a semiconductor device provided above the first conductive layer, a second conductive layer provided above the semiconductor device, a first via connecting the second conductive layer and the first conductive layer, a third conductive layer provided above the second conductive layer, a second via passing through the first opening, and an antenna provided above the third conductive layer. A dielectric is provided between the second conductive layer and the semiconductor device, between the third conductive layer and the second conductive layer, and between the antenna and the third conductive layer. The second conductive layer includes a first opening. The second via connects the third conductive layer and the first conductive layer.Type: ApplicationFiled: July 16, 2014Publication date: January 22, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Tadahiro SASAKI, Kazuhiko ITAYA, Hiroshi YAMADA, Yutaka ONOZUKA, Nobuto Managaki, Atsuko IIDA