Patents by Inventor Nobuya Takahashi

Nobuya Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220375679
    Abstract: To improve magnetic characteristics of a coil component having a structure in which an interlayer insulating film is provided between a spiral coil pattern and a magnetic element body. A coil component 1 includes: an interlayer insulating film 41 covering coil patterns CP1 to CP3 from one side in the axial direction of the coil patterns; a magnetic element body M1 filled in the inner diameter areas of the coil patterns CP1 to CP3; and a magnetic element body M2 covering the coil patterns CP1 to CP3 from the one side in the axial direction through the interlayer insulating film 41. The interlayer insulating film 41 has a protruding part 41A radially protruding to the inner diameter area, and the protruding part 41A is curved to the other side in the axial direction. Since the protruding part 41A is curved in the axial direction, the entrance of a magnetic path passing through the inner diameter area is made wider than when the protruding part 41A linearly protrudes to the inner diameter area.
    Type: Application
    Filed: September 29, 2020
    Publication date: November 24, 2022
    Inventors: Takuya TAKEUCHI, Naoaki FUJII, Nobuya TAKAHASHI
  • Patent number: 11476041
    Abstract: A coil component is provided with a coil part in which a plurality of conductor layers and a plurality of interlayer insulating layers are alternately laminated; and a sealing resin layer that covers the coil part. The conductor layers each include a spiral pattern. The interlayer insulating layers each cover an upper surface and a side surface of the spiral pattern. The recessed part is formed in the side wall surface of the interlayer insulating layer. A part of the sealing resin layer is embedded in the recessed part.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: October 18, 2022
    Assignee: TDK CORPORATION
    Inventors: Masanori Suzuki, Manabu Yamatani, Takuya Takeuchi, Ikuya Kokubo, Tomonaga Nishikawa, Naoaki Fujii, Nobuya Takahashi
  • Publication number: 20210233698
    Abstract: A coil component includes spiral conductor patterns S1 and S2 and insulating resin layers that cover the spiral conductor patterns S1 and S2, respectively. An outermost turn of the spiral conductor pattern S1 has a widened part. As a result, an outer wall surface part constituting the outer wall surface of the outermost turn in the radial direction and an outer wall surface part constituting the outer wall surface of the outermost turn of the spiral conductor pattern S2 in the radial direction differ in radial position from each other. Overlap of the insulating resin layers in the lamination direction is reduced to suppress thermal expansion or contraction of the insulating resin layers in the lamination direction at the overlap. This can relieve a stress applied to the interface between the spiral conductor pattern and the insulating resin layer.
    Type: Application
    Filed: June 5, 2019
    Publication date: July 29, 2021
    Inventors: Nobuya TAKAHASHI, Naoaki FUJII, Tomonaga NISHIKAWA
  • Patent number: 10840010
    Abstract: Disclosed herein is a coil component that includes a coil part in which a plurality of conductor layers and a plurality of interlayer insulting layers are alternately laminated, and an external terminal. Each of the conductor layers has a coil conductor pattern and an electrode pattern exposed from the coil part. The electrode patterns are connected to each other through a plurality of via conductors penetrating the interlayer insulating layers. At least one of the interlayer insulating layers is exposed from the coil part positioned between the plurality of electrode patterns. The external terminal is formed on the electrode patterns exposed from the coil part so as to avoid an exposed part of the interlayer insulating layer.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: November 17, 2020
    Assignee: TDK CORPORATION
    Inventors: Naoaki Fujii, Tomonaga Nishikawa, Kouji Kawamura, Nobuya Takahashi
  • Publication number: 20190244750
    Abstract: A coil component is provided with a coil part in which a plurality of conductor layers and a plurality of interlayer insulating layers are alternately laminated; and a sealing resin layer that covers the coil part. The conductor layers each include a spiral pattern. The interlayer insulating layers each cover an upper surface and a side surface of the spiral pattern. The recessed part is formed in the side wall surface of the interlayer insulating layer. A part of the sealing resin layer is embedded in the recessed part.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 8, 2019
    Applicant: TDK Corporation
    Inventors: Masanori SUZUKI, Manabu Yamatani, Takuya Takeuchi, Ikuya Kokubo, Tomonaga Nishikawa, Naoki Fujii, Nobuya Takahashi
  • Publication number: 20180323003
    Abstract: Disclosed herein is a coil component that includes a coil part in which a plurality of conductor layers and a plurality of interlayer insulting layers are alternately laminated, and an external terminal. Each of the conductor layers has a coil conductor pattern and an electrode pattern exposed from the coil part. The electrode patterns are connected to each other through a plurality of via conductors penetrating the interlayer insulating layers. At least one of the interlayer insulating layers is exposed from the coil part positioned between the plurality of electrode patterns. The external terminal is formed on the electrode patterns exposed from the coil part so as to avoid an exposed part of the interlayer insulating layer.
    Type: Application
    Filed: April 24, 2018
    Publication date: November 8, 2018
    Applicant: TDK CORPORATION
    Inventors: Naoaki FUJII, Tomonaga NISHIKAWA, Kouji KAWAMURA, Nobuya TAKAHASHI
  • Patent number: 9736945
    Abstract: A printed wiring board includes an insulation layer, conductive pads formed on the insulation layer and positioned to connect an electronic component, and a conductive wiring pattern including first and second conductive patterns and formed on the insulation layer such that the conductive wiring pattern is extending between the conductive pads. The first pattern includes first wiring lines, the second pattern includes second wiring lines, the first and second conductive patterns are formed such that the first wiring lines and the second wiring lines are alternately arrayed on the insulation layer, each of the first wiring lines includes a first metal layer formed on an interface with the insulation layer, each of the second wiring lines includes a second metal layer formed on an interface with the insulation layer, and the first metal layer includes a metal material which is different from a metal material forming the second metal layer.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 15, 2017
    Assignee: IBIDEN CO., LTD.
    Inventor: Nobuya Takahashi
  • Patent number: 9711439
    Abstract: A printed wiring board includes an insulating layer including insulating material, and a conductor layer formed on a surface of the insulating layer and including conductor pads and conductor patterns such that the conductor pads are positioned to connect one or more electronic components and that the conductor patterns are formed between the conductor pads. The conductor patterns are formed such that each conductor pattern has a pattern width of 3 ?m or less and that the conductor patterns have a pattern interval of 3 ?m or less between adjacent conductor patterns, and the insulating layer has recess portions formed on the surface between the conductor patterns at least along the conductor patterns such that the recess portions have a depth in a range of 0.1 ?m to 2.0 ?m relative to a contact interface at which the conductor patterns and the insulating layer are in contact with each other.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: July 18, 2017
    Assignee: IBIDEN CO., LTD.
    Inventors: Hajime Sakamoto, Nobuya Takahashi
  • Patent number: 9536801
    Abstract: An electronic component including a wiring board having interlayer insulation layers and conductive patterns, the wiring board having a first surface and a second surface on the opposite side of the first surface, multiple first bumps formed on a first conductive pattern positioned on the first surface of the wiring board among the conductive patterns of the wiring board, a semiconductor element mounted on the first surface of the wiring board through the first bumps, an encapsulating resin encapsulating the semiconductor element and at least a portion of a side surface of the wiring board, the side surface of the wiring board extending between the first surface and second surface of the wiring board, and multiple of second bumps formed on the second surface of the wiring board and connected to a second conductive pattern of the conductive patterns in the wiring board.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 3, 2017
    Assignee: IBIDEN CO., LTD.
    Inventors: Toshiki Furutani, Daiki Komatsu, Nobuya Takahashi
  • Patent number: 9480157
    Abstract: A wiring board includes a first interlayer insulation layer, a second interlayer insulation layer formed on the first interlayer insulation layer and having an opening portion, first conductive pads formed on the second interlayer insulation layer, a conductive plane layer formed on the first interlayer insulation layer such that the conductive plane layer is exposed by the opening portion of the second interlayer insulation layer, a wiring structure positioned directly on the conductive plane layer such that the wiring structure is accommodated in the opening portion of the second interlayer insulation layer, and second conductive pads formed on the wiring structure such that the first conductive pads and the second conductive pads are set to be positioned on a same plane.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: October 25, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Yoshinori Shizuno, Nobuya Takahashi, Hisayuki Nakagome, Asuka Ii
  • Patent number: 9338886
    Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: May 10, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Toshiki Furutani, Daiki Komatsu, Masatoshi Kunieda, Naomi Fujita, Nobuya Takahashi
  • Publication number: 20160066423
    Abstract: A printed wiring board includes an insulating layer including insulating material, and a conductor layer formed on a surface of the insulating layer and including conductor pads and conductor patterns such that the conductor pads are positioned to connect one or more electronic components and that the conductor patterns are formed between the conductor pads. The conductor patterns are formed such that each conductor pattern has a pattern width of 3 ?m or less and that the conductor patterns have a pattern interval of 3 ?m or less between adjacent conductor patterns, and the insulating layer has recess portions formed on the surface between the conductor patterns at least along the conductor patterns such that the recess portions have a depth in a range of 0.1 ?m to 2.0 ?m relative to a contact interface at which the conductor patterns and the insulating layer are in contact with each other.
    Type: Application
    Filed: September 1, 2015
    Publication date: March 3, 2016
    Applicant: IBIDEN CO., LTD.
    Inventors: Hajime SAKAMOTO, Nobuya TAKAHASHI
  • Publication number: 20160037629
    Abstract: A printed wiring board includes an insulation layer, conductive pads formed on the insulation layer and positioned to connect an electronic component, and a conductive wiring pattern including first and second conductive patterns and formed on the insulation layer such that the conductive wiring pattern is extending between the conductive pads. The first pattern includes first wiring lines, the second pattern includes second wiring lines, the first and second conductive patterns are formed such that the first wiring lines and the second wiring lines are alternately arrayed on the insulation layer, each of the first wiring lines includes a first metal layer formed on an interface with the insulation layer, each of the second wiring lines includes a second metal layer formed on an interface with the insulation layer, and the first metal layer includes a metal material which is different from a metal material forming the second metal layer.
    Type: Application
    Filed: July 30, 2015
    Publication date: February 4, 2016
    Applicant: IBIDEN CO., LTD.
    Inventor: Nobuya TAKAHASHI
  • Publication number: 20150255359
    Abstract: An electronic component including a wiring board having interlayer insulation layers and conductive patterns, the wiring board having a first surface and a second surface on the opposite side of the first surface, multiple first bumps formed on a first conductive pattern positioned on the first surface of the wiring board among the conductive patterns of the wiring board, a semiconductor element mounted on the first surface of the wiring board through the first bumps, an encapsulating resin encapsulating the semiconductor element and at least a portion of a side surface of the wiring board, the side surface of the wiring board extending between the first surface and second surface of the wiring board, and multiple of second bumps formed on the second surface of the wiring board and connected to a second conductive pattern of the conductive patterns in the wiring board.
    Type: Application
    Filed: May 22, 2015
    Publication date: September 10, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Toshiki FURUTANI, Daiki KOMATSU, Nobuya TAKAHASHI
  • Publication number: 20150245485
    Abstract: A printed wiring board includes a first insulating layer, a first conductor layer formed on a surface of the first insulating layer and including first pads, and a wiring structure including a second conductor layer formed on the first insulating layer, a second insulating layer laminated on the second conductor layer, a third conductor layer formed on the second insulating layer, and formed through the second insulating layer. The second conductor layer includes second pads formed on the first insulating layer, the third conductor layer includes third pads formed on the second insulating layer, the via conductors are positioned such that the via conductors are connecting the second pads and the third conductor layer, and the wiring structure is formed such that the second conductor layer and third conductor layer are not electrically connected to the first conductor layer.
    Type: Application
    Filed: February 23, 2015
    Publication date: August 27, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Nobuya TAKAHASHI, Shigeru YAMADA, Takashi KARIYA
  • Publication number: 20150216049
    Abstract: A wiring board includes a first interlayer insulation layer, a second interlayer insulation layer formed on the first interlayer insulation layer and having an opening portion, first conductive pads formed on the second interlayer insulation layer, a conductive plane layer formed on the first interlayer insulation layer such that the conductive plane layer is exposed by the opening portion of the second interlayer insulation layer, a wiring structure positioned directly on the conductive plane layer such that the wiring structure is accommodated in the opening portion of the second interlayer insulation layer, and second conductive pads formed on the wiring structure such that the first conductive pads and the second conductive pads are set to be positioned on a same plane.
    Type: Application
    Filed: April 7, 2015
    Publication date: July 30, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoshinori SHIZUNO, Nobuya TAKAHASHI, Hisayuki NAKAGOME, Asuka II
  • Patent number: 9059187
    Abstract: An electronic component including a wiring board having interlayer insulation layers and conductive patterns, the wiring board having a first surface and a second surface on the opposite side of the first surface, multiple first bumps formed on a first conductive pattern positioned on the first surface of the wiring board among the conductive patterns of the wiring board, a semiconductor element mounted on the first surface of the wiring board through the first bumps, an encapsulating resin encapsulating the semiconductor element and at least a portion of a side surface of the wiring board, the side surface of the wiring board extending between the first surface and second surface of the wiring board, and multiple of second bumps formed on the second surface of the wiring board and connected to a second conductive pattern of the conductive patterns in the wiring board.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: June 16, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Toshiki Furutani, Daiki Komatsu, Nobuya Takahashi
  • Patent number: 9035463
    Abstract: A wiring board includes a first insulation layer, a first conducive layer having first conductive patterns formed on the first insulation layer, a wiring structure positioned on the first insulation layer and including a second insulation layer and a second conductive layer having second conductive patterns formed on the second insulation layer, multiple conductive patterns formed on the wiring structures such that the conductive patterns are connected to the second conductive patterns, respectively, multiple first electrodes formed on the first conductive patterns, respectively, and multiple second electrodes formed on the conductive patterns connected to the second conductive patterns of the wiring structure, respectively. The first electrodes and the second electrodes have top surfaces which form the same plane.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: May 19, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Yoshinori Shizuno, Nobuya Takahashi, Hisayuki Nakagome, Asuka Ii
  • Publication number: 20140284820
    Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.
    Type: Application
    Filed: June 4, 2014
    Publication date: September 25, 2014
    Applicant: IBIDEN CO., LTD.
    Inventors: Toshiki FURUTANI, Daiki KOMATSU, Masatoshi KUNIEDA, Naomi FUJITA, Nobuya TAKAHASHI
  • Patent number: 8785255
    Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: July 22, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Toshiki Furutani, Daiki Komatsu, Masatoshi Kunieda, Naomi Fujita, Nobuya Takahashi