Abstract: An image forming apparatus includes: an image forming unit that forms an image onto a recording medium; an image reading unit that is disposed above the image forming unit in an up-down direction, transports a document, and reads an image formed on the document; a first output section that is provided in a connection section connecting the image forming unit and the image reading unit to each other in the up-down direction and to which the document read by the image reading unit and transported in a width direction of the image forming unit is output; a second output section that is provided below the first output section in the connection section and to which the recording medium having the image formed thereon by the image forming unit is output; and a rotating member that serves as a front portion of the first output section in a depth direction of the image forming unit, is rotatable by a rotating shaft disposed at an upstream side in an output direction of the document, and switches between an output pos

Abstract: A transport device includes: a container portion that accommodates a transportable member; a receiving portion disposed above or below the container portion to at least partially overlap the container portion in a plan view, to receive the transportable member; a transport path along which the transportable member accommodated in the container portion is transported to the receiving portion; a first enlargement portion disposed at the container portion, the first enlargement portion moving in a direction opposite to a transport direction in which the transportable member is transported from the container portion to the transport path to enlarge a container area in the container portion for receiving the transportable member; and a second enlargement portion disposed at the receiving portion, the second enlargement portion moving in the opposite direction in conjunction with a movement of the first enlargement portion in the opposite direction to enlarge a container area in the receiving portion for receiving

Abstract: A document reading device includes: a device body; a transport path that is provided in the device body and through which a document is transported; a reading unit that is provided in the device body, has a reading surface, and reads an image of a document transported through the transport path; a moving part that is provided in the device body and is capable of being moved to a covering position at which the moving part covers the reading surface and to an exposing position at which the moving part exposes the reading surface; a first opening and closing part that is provided on the device body so as to be opened and closed and opens the transport path, at a first opening position; and a second opening and closing part that is provided beside the device body so as to be opened and closed or so as to be removable and mountable and exposes the moving part, at a second opening position or a removal position.

Abstract: An information processing device 30 configured to transmit a file stored in a memory medium 120 to a terminal. The information processing device includes: a specifying information creating unit 34 configured to create specifying information for specifying files stored in the memory medium, by using a file name and information about the memory medium; a transmitting unit 35 configured to transmit the specifying information to the terminal; and a file transmitting unit 37 configured to transmit to the terminal one of the files specified by the terminal in accordance with the specifying information.

Abstract: An information processing device 30 configured to transmit a file stored in a memory medium 120 to a terminal. The information processing device includes: a specifying information creating unit 34 configured to create specifying information for specifying files stored in the memory medium, by using a file name and information about the memory medium; a transmitting unit 35 configured to transmit the specifying information to the terminal; and a file transmitting unit 37 configured to transmit to the terminal one of the files specified by the terminal in accordance with the specifying information.

Abstract: A sheet processing apparatus includes a feed-in path through which a sheet is fed, a first transport path through which a sheet fed from the feed-in path is transported, and a second transport path through which a sheet fed from the feed-in path is transported. The sheet processing apparatus also includes the following elements. A first processor sequentially stacks sheets output from the first transport path and performs first processing on a bundle of stacked sheets. A second processor sequentially stacks sheets output from the second transport path and performs second processing, which is different from the first processing, on a bundle of stacked sheets. A common retention path causes a sheet fed through the feed-in path to temporarily remain on the common retention path and causes the sheet temporarily remaining on the common retention path to be output to one of the first and second transport paths.

Abstract: A sheet processing apparatus includes a feed-in path through which a sheet is fed, a first transport path through which a sheet fed from the feed-in path is transported, and a second transport path through which a sheet fed from the feed-in path is transported. The sheet processing apparatus also includes the following elements. A first processor sequentially stacks sheets output from the first transport path and performs first processing on a bundle of stacked sheets. A second processor sequentially stacks sheets output from the second transport path and performs second processing, which is different from the first processing, on a bundle of stacked sheets. A common retention path causes a sheet fed through the feed-in path to temporarily remain on the common retention path and causes the sheet temporarily remaining on the common retention path to be output to one of the first and second transport paths.

Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.

Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.

Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.

Abstract: After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.

Abstract: After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.

Abstract: To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.

Abstract: A semiconductor device includes a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, semiconductor elements being electrically isolated from each other by the isolation film. The semiconductor device also includes a PN junction portion provided under the isolation film and formed by two semiconductor regions of different conductivity types in the semiconductor layer. The isolation film includes a nitride film provided in a position corresponding to a top of the PN junction portion and has a substantially uniform thickness across the two semiconductor regions and an upper oxide film and a lower oxide film which are provided in upper and lower portions of the nitride film. The surface of the semiconductor layer is silicidized in such a state that a surface of the isolation film is exposed.

Abstract: A boat (4) has a recess (5) for supporting a laminated wafer (50). The recess (5) has a first side surface (5a), a first bottom surface (5b), a second side surface (5c), a second bottom surface (5d) and a third side surface (5e). Viewing from an upper surface of the boat (4), the second bottom surface (5d) is located in a position lower than the first bottom surface (5b). The laminated wafer (50) is mounted on the boat (4) in the state that a side surface of a first silicon wafer (1) is not in contact with the second bottom surface (5d) of the recess (5) and a side surface of a second silicon wafer (2) is in contact with the first bottom surface (5b) of the recess (5). A second main surface (2a) of the second silicon wafer (2) is in contact with the first side surface (5a) of the recess (5) and a second main surface (1a) of the first silicon wafer (1) is in contact with the third side surface (5e) of the recess (5).

Abstract: A computer-implemented method of process analysis allows for accurate analysis of the degree of achievement of a predetermined effect exhibited by a predetermined process included in a manufacturing operation. In a step S2, a first manufacturing operation including a predetermined cleaning process is performed to form chips on wafers to be cleaned. In a step S3, a second manufacturing operation including details identical to those of the first manufacturing operation except the predetermined cleaning process is performed to form chips on wafers not to be cleaned. In a step S4, an electric tester is applied to all the chips formed on the wafers to be cleaned and the wafers not to be cleaned, to determine the quality of each chip. In a step S5, all the chips are classified into four categories according to the kind of wafer (i.e., the wafer to be cleaned or the wafer not to be cleaned) and the quality as determined of each chip.

Abstract: In the step (S11), chip classification data in which a plurality of chips are classified into four sorts on the basis of presence/absence of (new) defects and pass/fail (of integrated circuits) is obtained. Next, in the step (S12) set is a situation where chips are randomly extracted out of all the chips with the number of chips with defect used as random extraction number on the basis of the chip classification data obtained in the step (S11). After that, in the step (S13) obtained is the random probability of failure (P(N4)) which is a probability that the number of faulty chips included in the randomly-extracted chips should be not less than the equivalent of the number (N4) of faulty chips with defect. Thus obtained is a defect analysis method and a method of verifying chip classification data, by which the analysis result on the basis of the chip classification data can be enhanced.

Abstract: To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.

Abstract: A semiconductor device that prevents metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film, a polysilicon film selectively provided on the trench isolation oxide film, a silicon layer provided on the polysilicon film, and a side wall spacer provided on a side surface of the polysilicon film. The polysilicon film is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region and an N-type well region in a SOI layer across the two well regions.

Abstract: A computer-implemented method of process analysis allows for accurate analysis of the degree of achievement of a predetermined effect exhibited by a predetermined process included in a manufacturing operation. In a step S2, a first manufacturing operation including a predetermined cleaning process is performed to form chips on wafers to be cleaned. In a step S3, a second manufacturing operation including details identical to those of the first manufacturing operation except the predetermined cleaning process is performed to form chips on wafers not to be cleaned. In a step S4, an electric tester is applied to all the chips formed on the wafers to be cleaned and the wafers not to be cleaned, to determine the quality of each chip. In a step S5, all the chips are classified into four categories according to the kind of wafer (i.e., the wafer to be cleaned or the wafer not to be cleaned) and the quality as determined of each chip.