Abstract: In the step (S11), chip classification data in which a plurality of chips are classified into four sorts on the basis of presence/absence of (new) defects and pass/fail (of integrated circuits) is obtained. Next, in the step (S12) set is a situation where chips are randomly extracted out of all the chips with the number of chips with defect used as random extraction number on the basis of the chip classification data obtained in the step (S11). After that, in the step (S13) obtained is the random probability of failure (P(N4)) which is a probability that the number of faulty chips included in the randomly-extracted chips should be not less than the equivalent of the number (N4) of faulty chips with defect. Thus obtained is a defect analysis method and a method of verifying chip classification data, by which the analysis result on the basis of the chip classification data can be enhanced.

Abstract: A boat (4) has a recess (5) for supporting a laminated wafer (50). The recess (5) has a first side surface (5a), a first bottom surface (5b), a second side surface (5c), a second bottom surface (5d) and a third side surface (5e). Viewing from an upper surface of the boat (4), the second bottom surface (5d) is located in a position lower than the first bottom surface (5b). The laminated wafer (50) is mounted on the boat (4) in the state that a side surface of a first silicon wafer (1) is not in contact with the second bottom surface (5d) of the recess (5) and a side surface of a second silicon wafer (2) is in contact with the first bottom surface (5b) of the recess (5). A second main surface (2a) of the second silicon wafer (2) is in contact with the first side surface (5a) of the recess (5) and a second main surface (1a) of the first silicon wafer (1) is in contact with the third side surface (5e) of the recess (5).

Abstract: A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle around (1)} non-defective chip with no new defect; {circle around (2)} defective chip with no new defect; {circle around (3)} non-defective chip with new defect; and {circle around (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.

Abstract: First, a silicon germanium single-crystalline layer and a silicon single-crystalline layer are formed on a main surface of a bond wafer by epitaxy. The overall surface of the bond wafer is oxidized for forming a silicon oxide layer. Then, a base wafer is bonded to the bond wafer. The bond wafer and the base wafer bonded to each other are heated for reinforcing adhesion therebetween. Then, the bond wafer is removed by plasma etching with chlorine gas while making the silicon germanium single-crystalline layer serve as a stopper. Thereafter the silicon germanium single-crystalline layer is polished by chemical mechanical polishing to have a thickness suitable for forming a device. Thus implemented is a method of manufacturing an SOI substrate by bonding capable of employing a layer having a crystal state with small irregularity for serving as a stopper having selectivity for single-crystalline silicon and effectively using the stopper as a device forming layer.

Abstract: To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.

Abstract: First, a silicon germanium single-crystalline layer and a silicon single-crystalline layer are formed on a main surface of a bond wafer by epitaxy. The overall surface of the bond wafer is oxidized for forming a silicon oxide layer. Then, a base wafer is bonded to the bond wafer. The bond wafer and the base wafer bonded to each other are heated for reinforcing adhesion therebetween. Then, the bond wafer is removed by plasma etching with chlorine gas while making the silicon germanium single-crystalline layer serve as a stopper. Thereafter the silicon germanium single-crystalline layer is polished by chemical mechanical polishing to have a thickness suitable for forming a device. Thus implemented is a method of manufacturing an SOI substrate by bonding capable of employing a layer having a crystal state with small irregularity for serving as a stopper having selectivity for single-crystalline silicon and effectively using the stopper as a device forming layer.

Abstract: First, a silicon germanium single-crystalline layer and a silicon single-crystalline layer are formed on a main surface of a bond wafer by epitaxy. The overall surface of the bond wafer is oxidized for forming a silicon oxide layer. Then, a base wafer is bonded to the bond wafer. The bond wafer and the base wafer bonded to each other are heated for reinforcing adhesion therebetween. Then, the bond wafer is removed by plasma etching with chlorine gas while making the silicon germanium single-crystalline layer serve as a stopper. Thereafter the silicon germanium single-crystalline layer is polished by chemical mechanical polishing to have a thickness suitable for forming a device. Thus implemented is a method of manufacturing an SOI substrate by bonding capable of employing a layer having a crystal state with small irregularity for serving as a stopper having selectivity for single-crystalline silicon and effectively using the stopper as a device forming layer.

Abstract: A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle around (1)} non-defective chip with no new defect; {circle around (2)} defective chip with no new defect; {circle around (3)} non-defective chip with new defect; and {circle around (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.

Abstract: A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle over (1)} non-defective chip with no new defect; {circle over (2)} defective chip with no new defect; {circle over (3)} non-defective chip with new defect; and {circle over (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.

Abstract: A semiconductor device and a semiconductor storage device having an SOI structure and being enable sufficient gettering performance without imposing limitations on the freedom of design of an LSI circuit. A semiconductor device includes a semiconductor wafer of SOI structure which has a insulation layer and a silicon layer provided thereon, wherein the semiconductor wafer includes a plurality of element fabrication regions where semiconductor elements are fabricated, and a cutting region provided between the element fabrication regions. Gettering sites are formed in the cutting region by means of embedding a gettering member into grooves of predetermined depth.

Abstract: A quality management system (S100) comprises a data processing unit (11), a processed-data judgment unit (12) receiving an output from the data processing unit (11), a sampling unit (13) receiving an output from the processed-data judgment unit (12), a file making unit (14) receiving an output from the sampling unit (13), a data processing unit (15) receiving an output from an observation unit (20) and a processed-data judgment unit (16) receiving an output from the data processing unit (15). The system (S100) having this constitution allows reduction in labor and time from finding of a defect to recognition of occurrence of abnormal condition and improvement in accuracy of fatality rate of the defect.

Abstract: An ordinary user can easily learn a step at which a problem occurs during semiconductor manufacturing processes and improve the yield of manufacturing products and the quality of the products. At a certain in-line inspection step, a CPU (3) stores data signals (V1) taken by an inspection apparatus (1) into a memory (2), and reads a result (V6) obtained at a precedent step and stores the same in the memory (2). The CPU (3) reads stored data signals (V2) from the memory (2), performs comparison or referral on data about defects which are detected at a current step and the result (V6) regarding the precedent step, and generates a defect data analysis processing result signal (V5) regarding the current step. The result (V5) consists of disappeared defect data, common defect data, new defect data to which a label of a current step number is assigned, and reappeared defect data.

Abstract: Method for detecting and examining a slightly irregular surface state is provided which includes the steps of: illuminating a surface of a sample with light beam for detecting the slightly irregular surface state; observing a variation of the light beam occurring due to the slightly irregular surface state to specify the location of the slightly irregular surface state in an x-y plane of the sample; making the location of a probe needle of a scanning probe microscope and the location of the slightly irregular surface state on the sample coincide with each other; and measuring a three-dimensional image of the slightly irregular surface state by means of the scanning probe microscope. The scanning probe microscope for use in the aforementioned method and a method for fabricating a semiconductor device or a liquid crystal display device which utilizes the aforementioned method are also provided.

Abstract: A cleaning device for semiconductor wafers includes a cleaning vessel, a frozen particle supply unit, a jet nozzle for ejecting the frozen particles toward the semiconductor wafer supported within the cleaning vessel, an exhaust duct coupled to the cleaning vessel, and an exhaust blower. First and second exhausts guide to the exhaust duct frozen particles and contaminants from within the cleaning vessel near the wafer and near the walls of the vessel, respectively. The first exhaust includes a first exhaust guide pipe whose upper and lower ends open to an interior of the cleaning vessel near the wafer and to the exhaust duct, respectively. The second exhaust may include a tapered exhaust guide pipe surrounding the first exhaust guide pipe or a plurality of exhaust guide pipes disposed circumferentially uniformly around the first exhaust guide pipe.

Abstract: A continuous rainwater monitoring device for effecting automatic chemical analysis of the rainwater. The device comprises, in addition to a funnel-shaped receiver-container, a rain gauge, a measurement and analysis means, and an automatic recorder, the following: a showering ring disposed above the receiver-container and supplied with a cleaning water from a cleaning water source; a cleaning evaluation means including an electrical resistivity meter; and a rainfall sensor for detecting the commencements and ends of rainfalls. During the time when there is no rainfall, the receiver-container and the rain gauge are filled with cleaning water supplied from the cleaning water source via the showering ring.

Abstract: An apparatus for counting particles attached to surfaces of a solid is disclosed which includes an external tank, an internal tank disposed within the external tank for hermetically accommodating a measuring liquid into which a sample having particles attached to the surfaces thereof is to be immersed, a driving mechanism for rotating the internal tank with respect to the external tank, sonic wave generators provided on the external tank for generating sonic waves having a plurality of different frequencies toward the internal tank, and a measuring mechanism connectable to the internal tank in a hermetic fashion for counting the number of particles in the measuring liquid removed from the sample by the sonic waves generated from the sonic wave generators.