Patents by Inventor Nobuyoshi Saito
Nobuyoshi Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942545Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.Type: GrantFiled: July 27, 2022Date of Patent: March 26, 2024Assignee: Kioxia CorporationInventors: Yuta Sato, Tomomasa Ueda, Nobuyoshi Saito, Keiji Ikeda
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Publication number: 20240087616Abstract: A semiconductor memory device comprises: memory layers arranged in a first direction; and a first and a second via wirings having different positions in a second direction. The memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring; and an electrode provided in a current path between the second transistor and the wiring. The second transistor comprises: a semiconductor layer electrically connected to the electrode and the second via wiring; and a gate electrode facing the semiconductor layer. The semiconductor layer faces at least one of surfaces on one side or the other side in the first direction of the gate electrode. The electrode includes a portion arranged with the second via wiring in a third direction.Type: ApplicationFiled: September 8, 2023Publication date: March 14, 2024Applicant: Kioxia CorporationInventors: Takafumi MASUDA, Nobuyoshi SAITO, Mutsumi OKAJIMA, Keiji IKEDA
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Publication number: 20240081042Abstract: A semiconductor memory device comprises: a first memory layer; and a first via wiring and a second via wiring extending in a first direction, and having different positions from each other in a second direction. The first memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a first wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring and the first wiring; a first electrode electrically connected to the second transistor; and a second electrode electrically connected to the first wiring and first electrode. A length of the second electrode in the first direction is larger than one or both of a length of the first wiring in the first direction and a length of the first conductive layer in the first direction.Type: ApplicationFiled: September 1, 2023Publication date: March 7, 2024Applicant: Kioxia CorporationInventors: Takafumi MASUDA, Mutsumi OKAJIMA, Nobuyoshi SAITO, Keiji IKEDA
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Publication number: 20240038280Abstract: A semiconductor memory device comprises: memory layers arranged in a first direction; and a first wiring extending in the first direction. The memory layers each comprise: a memory portion; a transistor; and a second wiring. The transistor comprises: a semiconductor layer electrically connected between the memory portion and the first wiring; a gate electrode facing the semiconductor layer and electrically connected to the second wiring; and a gate insulating film provided between the semiconductor layer and the gate electrode. The semiconductor layer faces surfaces of the gate electrode on one side and the other side in the first direction. In a cross section perpendicular to the first direction and including a part of the transistor corresponding to one of the memory layers, the first wiring comprises: a first surface in contact with the transistor; and a second surface not in contact with the transistor.Type: ApplicationFiled: March 16, 2023Publication date: February 1, 2024Applicant: Kioxia CorporationInventors: Takafumi MASUDA, Mutsumi OKAJIMA, Nobuyoshi SAITO, Keiji IKEDA
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Publication number: 20230309294Abstract: A semiconductor device includes: an oxide semiconductor layer extending in a first direction; a gate electrode overlapping the oxide semiconductor layer in a second direction intersecting the first direction; a gate insulating film provided between the gate electrode and the oxide semiconductor layer; a first conductive layer provided on the oxide semiconductor layer in the first direction and containing a conductive oxide; a second conductive layer provided on the first conductive layer in the first direction and containing a metal element; a first protective film in contact with a side surface of the second conductive layer; and a second protective film in contact with at least a part of a side surface or an upper surface of the first conductive layer. The first protective film and the second protective film each contain a material having an oxygen diffusion coefficient smaller than that of the second conductive layer.Type: ApplicationFiled: September 1, 2022Publication date: September 28, 2023Applicant: Kioxia CorporationInventors: Mutsumi OKAJIMA, Nobuyoshi SAITO, Keiji IKEDA, Kotaro NODA, Takanori AKITA
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Patent number: 11769810Abstract: A semiconductor device according to an embodiment includes an oxide semiconductor layer, a gate electrode, and the gate electrode, a first electrode electrically connected to the oxide semiconductor layer, a second electrode electrically connected to the oxide semiconductor layer, a first conductive layer provided at at least one position between the oxide semiconductor layer and the first electrode and between the oxide semiconductor layer and the second electrode, the first conductive layer containing a first metal element, a first element different from the first metal element, and one of oxygen (O) or nitrogen (N), and a second conductive layer between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing oxygen (O) and a second element different from both of the first metal element and the first element. The gate electrode is between the first electrode and the second electrode in the first direction.Type: GrantFiled: March 11, 2021Date of Patent: September 26, 2023Assignee: Kioxia CorporationInventors: Junji Kataoka, Tomomasa Ueda, Shushu Zheng, Nobuyoshi Saito, Keiji Ikeda
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Publication number: 20220406934Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.Type: ApplicationFiled: July 27, 2022Publication date: December 22, 2022Applicant: Kioxia CorporationInventors: Yuta SATO, Tomomasa UEDA, Nobuyoshi SAITO, Keiji IKEDA
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Publication number: 20220302120Abstract: A semiconductor device of an embodiment is provided with: an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; a first conductive layer provided at least one of positions between the first region and the first electrode or between the second region and the second electrode and containing a first metal element and at least one element of oxygen (O) or nitrogen (N); and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer and containing oxygen (O) and at least one element selected from indium (In), zinc (Zn), tin (Sn), or cadmium (Cd). The second conductive layer is thicker than the first conductive layer.Type: ApplicationFiled: September 9, 2021Publication date: September 22, 2022Applicant: Kioxia CorporationInventors: Yuta SATO, Tomomasa UEDA, Nobuyoshi SAITO, Keiji IKEDA
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Patent number: 11430886Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.Type: GrantFiled: March 11, 2021Date of Patent: August 30, 2022Assignee: KIOXIA CORPORATIONInventors: Yuta Sato, Tomomasa Ueda, Nobuyoshi Saito, Keiji Ikeda
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Publication number: 20220085212Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.Type: ApplicationFiled: March 11, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Yuta SATO, Tomomasa UEDA, Nobuyoshi SAITO, Keiji IKEDA
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Publication number: 20220085182Abstract: A semiconductor device according to an embodiment includes an oxide semiconductor layer, a gate electrode, and the gate electrode, a first electrode electrically connected to the oxide semiconductor layer, a second electrode electrically connected to the oxide semiconductor layer, a first conductive layer provided at at least one position between the oxide semiconductor layer and the first electrode and between the oxide semiconductor layer and the second electrode, the first conductive layer containing a first metal element, a first element different from the first metal element, and one of oxygen (O) or nitrogen (N), and a second conductive layer between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing oxygen (O) and a second element different from both of the first metal element and the first element. The gate electrode is between the first electrode and the second electrode in the first direction.Type: ApplicationFiled: March 11, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Junji KATAOKA, Tomomasa UEDA, Shushu ZHENG, Nobuyoshi SAITO, Keiji IKEDA
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Patent number: 11024719Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor channel, an insulation layer, an oxide layer, and a gate electrode. The oxide semiconductor channel includes a portion extending along a first direction and connects the first electrode to the second electrode. The insulation layer surrounds the oxide semiconductor channel. The oxide layer covers the oxide semiconductor channel and the insulation layer, and includes an oxide of a metal element. The gate electrode covers the oxide semiconductor channel, the insulation layer, and the oxide layer, and includes the metal element.Type: GrantFiled: September 6, 2019Date of Patent: June 1, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoaki Sawabe, Nobuyoshi Saito, Junji Kataoka, Tomomasa Ueda, Keiji Ikeda
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Patent number: 10950735Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer and a first layer. The semiconductor layer includes a first portion including a first element and oxygen. The first element includes at least one selected from the group consisting of In, Ga, Zn, Al, Sn, Ti, Si, Ge, Cu, As, and W. The first layer includes a second element including at least one selected from the group consisting of W, Ti, Ta, Mo, Cu, Al, Ag, Hf, Au, Pt, Pd, Ru, Y, V, Cr, Ni, Nb, In, Ga, Zn, and Sn. The first portion includes a first region and a second region. The second region is provided between the first region and the first layer. The first region includes a bond of the first element and oxygen. The second region includes a bond of the first element and a metallic element.Type: GrantFiled: March 12, 2019Date of Patent: March 16, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Junji Kataoka, Tomomasa Ueda, Tomoaki Sawabe, Keiji Ikeda, Nobuyoshi Saito
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Patent number: 10790396Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and extending in a first direction; a gate electrode surrounding the oxide semiconductor layer; and a first gate insulating layer provided between the gate electrode and the oxide semiconductor layer, the first gate insulating layer surrounding the oxide semiconductor layer, and the first gate insulating layer having a length in the first direction shorter than a length of the oxide semiconductor layer in the first direction.Type: GrantFiled: August 14, 2018Date of Patent: September 29, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoaki Sawabe, Tomomasa Ueda, Keiji Ikeda, Tsutomu Tezuka, Nobuyoshi Saito
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Publication number: 20200303554Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor channel, an insulation layer, an oxide layer, and a gate electrode. The oxide semiconductor channel includes a portion extending along a first direction and connects the first electrode to the second electrode. The insulation layer surrounds the oxide semiconductor channel. The oxide layer covers the oxide semiconductor channel and the insulation layer, and includes an oxide of a metal element. The gate electrode covers the oxide semiconductor channel, the insulation layer, and the oxide layer, and includes the metal element.Type: ApplicationFiled: September 6, 2019Publication date: September 24, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tomoaki SAWABE, Nobuyoshi SAITO, Junji KATAOKA, Tomomasa UEDA, Keiji IKEDA
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Patent number: 10714629Abstract: According to one embodiment, a transistor includes first to third conductors, first and second oxide semiconductors, and a gate insulating film. The first and second conductors are stacked via an insulator above a substrate. The first oxide semiconductor is formed on the first conductor. The second oxide semiconductor is formed on the first oxide semiconductor. The second oxide semiconductor have a pillar shape through the second conductor along a first direction crossing a surface of the substrate. The second oxide semiconductor is different from the first oxide semiconductor. The gate insulating film is formed between the second conductor and the second oxide semiconductor. The third conductor is formed on the second oxide semiconductor.Type: GrantFiled: September 5, 2018Date of Patent: July 14, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Nobuyoshi Saito, Tomomasa Ueda, Kentaro Miura, Keiji Ikeda, Tsutomu Tezuka
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Patent number: 10553601Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.Type: GrantFiled: July 20, 2018Date of Patent: February 4, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsutomu Tezuka, Fumitaka Arai, Keiji Ikeda, Tomomasa Ueda, Nobuyoshi Saito, Chika Tanaka, Kentaro Miura, Tomoaki Sawabe
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Publication number: 20200013892Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer and a first layer. The semiconductor layer includes a first portion including a first element and oxygen. The first element includes at least one selected from the group consisting of In, Ga, Zn, Al, Sn, Ti, Si, Ge, Cu, As, and W. The first layer includes a second element including at least one selected from the group consisting of W, Ti, Ta, Mo, Cu, Al, Ag, Hf, Au, Pt, Pd, Ru, Y, V, Cr, Ni, Nb, In, Ga, Zn, and Sn. The first portion includes a first region and a second region. The second region is provided between the first region and the first layer. The first region includes a bond of the first element and oxygen. The second region includes a bond of the first element and a metallic element.Type: ApplicationFiled: March 12, 2019Publication date: January 9, 2020Applicant: Toshiba Memory CorporationInventors: Junji KATAOKA, Tomomasa UEDA, Tomoaki SAWABE, Keiji IKEDA, Nobuyoshi SAITO
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Patent number: 10497712Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.Type: GrantFiled: July 20, 2018Date of Patent: December 3, 2019Assignee: Toshiba Memory CorporationInventors: Tsutomu Tezuka, Fumitaka Arai, Keiji Ikeda, Tomomasa Ueda, Nobuyoshi Saito, Chika Tanaka, Kentaro Miura, Tomoaki Sawabe
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Publication number: 20190296155Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and extending in a first direction; a gate electrode surrounding the oxide semiconductor layer; and a first gate insulating layer provided between the gate electrode and the oxide semiconductor layer, the first gate insulating layer surrounding the oxide semiconductor layer, and the first gate insulating layer having a length in the first direction shorter than a length of the oxide semiconductor layer in the first direction.Type: ApplicationFiled: August 14, 2018Publication date: September 26, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tomoaki SAWABE, Tomomasa UEDA, Keiji IKEDA, Tsutomu TEZUKA, Nobuyoshi SAITO