Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer and a first layer. The semiconductor layer includes a first portion including a first element and oxygen. The first element includes at least one selected from the group consisting of In, Ga, Zn, Al, Sn, Ti, Si, Ge, Cu, As, and W. The first layer includes a second element including at least one selected from the group consisting of W, Ti, Ta, Mo, Cu, Al, Ag, Hf, Au, Pt, Pd, Ru, Y, V, Cr, Ni, Nb, In, Ga, Zn, and Sn. The first portion includes a first region and a second region. The second region is provided between the first region and the first layer. The first region includes a bond of the first element and oxygen. The second region includes a bond of the first element and a metallic element.

Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.

Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and extending in a first direction; a gate electrode surrounding the oxide semiconductor layer; and a first gate insulating layer provided between the gate electrode and the oxide semiconductor layer, the first gate insulating layer surrounding the oxide semiconductor layer, and the first gate insulating layer having a length in the first direction shorter than a length of the oxide semiconductor layer in the first direction.

Abstract: According to one embodiment, a transistor includes first to third conductors, first and second oxide semiconductors, and a gate insulating film. The first and second conductors are stacked via an insulator above a substrate. The first oxide semiconductor is formed on the first conductor. The second oxide semiconductor is formed on the first oxide semiconductor. The second oxide semiconductor have a pillar shape through the second conductor along a first direction crossing a surface of the substrate. The second oxide semiconductor is different from the first oxide semiconductor. The gate insulating film is formed between the second conductor and the second oxide semiconductor. The third conductor is formed on the second oxide semiconductor.

Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

Abstract: According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.

Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.

Abstract: According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.

Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

Abstract: According to one embodiment, a semiconductor memory includes: a first gate of a first select transistor and a second gate of a second select transistor on a gate insulating film on a semiconductor layer; an oxide semiconductor layer above the semiconductor layer; a first control gate of a first cell and a second control gate of a second cell on an insulating layer on the oxide semiconductor layer; a third gate of a first transistor between the first control gate and the second control gate; a fourth gate of a second transistor between a first end of the oxide semiconductor layer and the second control gate; an interconnect connected to the first end; a source line connected to the first select transistor; and a bit line connected to the second select transistor.

Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer. The third semiconductor is provided between the first semiconductor layer and the second semiconductor layer. A first transistor includes a first gate electrode and a first amorphous semiconductor layer. The first gate electrode and the first amorphous semiconductor layer overlap in a first direction. The first direction is from the first semiconductor layer toward the second semiconductor layer. The first gate electrode is provided between the second semiconductor layer and the first amorphous semiconductor layer.

Abstract: According to one embodiment, an oxide semiconductor includes indium, gallium, and silicon. A concentration of the silicon in the oxide semiconductor is not less than 7 atomic percent and not more than 11 atomic percent.

Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor transistor. The oxide semiconductor transistor includes a semiconductor layer including an oxide semiconductor, the semiconductor layer including a source region and a source electrode. The source electrode includes a source conductive layer including copper, a first tantalum-containing region provided between the source conductive layer and the source region, the first tantalum-containing region including tantalum, a first low nitrogen composition region provided between the first tantalum-containing region and the source region, the first low nitrogen composition region including Ta1?x1Nx1 (0<x1<0.5), and a first high nitrogen composition region provided between the first low nitrogen composition region and the source region, the first high nitrogen composition region including Ta1?x2Nx2 (0.5?x2<1).

Abstract: According to one embodiment, an oxide semiconductor includes indium, gallium, and silicon. A concentration of the silicon in the oxide semiconductor is not less than 7 atomic percent and not more than 11 atomic percent.

Abstract: According to one embodiment, a method for manufacturing a display element is disclosed. The method can include forming a peeling layer, forming a resin layer, forming a barrier layer, forming an interconnect layer, forming a display layer, and removing. The peeling layer is formed on a major surface of a base body. The major surface has first, second, and third regions. The peeling layer includes first, second, and third peeling portions. The resin layer is formed on the peeling layer. The resin layer includes first and second resin portions. The barrier layer is formed on the first, second, and third peeling portions. The interconnect layer is formed on the barrier layer. The display layer is formed on the interconnect layer. The first peeling portion is removed from the first resin portion and the second peeling portion is removed from the second resin portion.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a first semiconductor portion and a second semiconductor portion being continuous with the first semiconductor portion, a first gate electrode, a second gate electrode, an insulating film. The first semiconductor portion includes a first portion, a second portion and a third portion provided between the first portion and the second portion. The second semiconductor portion includes a fourth portion separated from the first portion, a fifth portion separated from the second portion, and a sixth portion provided between the forth portion and the fifth portion. The first gate electrode is separated from the third portion. The second gate electrode is separated from the sixth portion. The insulating film is provided at a first position between the first gate electrode and the semiconductor layer and at a second position between the second gate electrode and the semiconductor layer.

Abstract: A semiconductor device includes a substrate having a major surface and a thin film transistor on the substrate. The thin film transistor includes an oxynitride semiconductor layer, first and second conductive layers, a first gate electrode and a first insulating layer. The oxynitride semiconductor layer includes a first portion electrically connected to the first conductive layer, a second portion electrically connected to the second conductive layer, and a third portion provided between the first and second portions. The oxynitride semiconductor layer includes indium, gallium, zinc, and nitrogen, a nitrogen content of the oxynitride semiconductor layer being 2 atomic % or less, and a gallium content of the oxynitride semiconductor layer is more than the nitrogen content. The first gate electrode is separated from the third portion in a direction intersecting the first direction; and the first insulating layer is provided between the third portion and the first gate electrode.

Abstract: According to an embodiment, an input device includes the following elements. The flexible touch panel includes a sensor area. The touch position detector detects a touch position on the sensor area to generate a detection signal. The deformation position detector detects a deformation position where a deformation amount is not less than a threshold on the sensor area. The input rejection area determination unit determines, based on the deformation position, an input rejection area. The input signal generator fails to output the detection signal as an input signal if the touch position is detected in the input rejection area, and outputs the detection signal as an input signal if the touch position is detected in an area other than the input rejection area.