Patents by Inventor Nobuyuki Endo
Nobuyuki Endo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8466403Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.Type: GrantFiled: December 21, 2010Date of Patent: June 18, 2013Assignee: Canon Kabushiki KaishaInventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
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Patent number: 8455001Abstract: The invention provides a cellulose derivative having a repeating unit of the formula below, a composition including the cellulose derivative and a phospholipid, a method for production thereof, and an adhesion barrier including the cellulose derivative or the composition. In the formula, R1, R2, and R3 are —H, —CH2—COOH, —CH2—COOX, or —CH2CO-phosphatidylethanolamine, and X is an alkali metal or an alkali earth metal. The degree of substitution of —CH2—COOH and —CH2—COOX is 0.3 to 2.0 in total, and the degree of substitution of —CH2CO-phosphatidylethanolamine is 0.001 to 0.05.Type: GrantFiled: February 6, 2008Date of Patent: June 4, 2013Assignee: Teijin LimitedInventors: Masaya Ito, Hiroaki Kaneko, Yukako Fukuhira, Nobuyuki Endo
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Publication number: 20130105663Abstract: A member for a solid-state image pickup device having a bonding plane with no gaps and a method for manufacturing the same are provided. The manufacturing method includes the steps of providing a first substrate provided with a photoelectric converter on its primary face and a first wiring structure, providing a second substrate provided with a part of a peripheral circuit on its primary face and a second wiring structure, and performing bonding so that the first substrate, the first wiring structure, the second wiring structure, and the second substrate are disposed in this order. In addition, at least one of an upper face of the first wiring structure and an upper face of the second wiring structure has a concave portion, and a conductive material forms a bottom face of the concave portion.Type: ApplicationFiled: July 4, 2011Publication date: May 2, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Junji Iwata
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Patent number: 8384177Abstract: A semiconductor device has an active region formed on a semiconductor substrate, a trench-type element isolation region formed on the semiconductor substrate, and a diffusion region in which fluorine is diffused that surrounds the element isolation region and is formed on the semiconductor substrate so as not to contact the active region.Type: GrantFiled: September 16, 2010Date of Patent: February 26, 2013Assignee: Canon Kabushiki KaishaInventor: Nobuyuki Endo
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Publication number: 20120286140Abstract: Dark current from a transfer transistor is suppressed and power-supply voltage in a second semiconductor substrate is lowered. A solid-state image pickup device includes a pixel array, a plurality of common output lines receiving signals read out from a plurality of pixels, a transfer scanning unit sequentially driving the plurality of transfer transistors, a signal processing unit processing the signals output to the common signal lines, and a level shift unit making amplitude of a pulse supplied to a gate of the transfer transistor larger than amplitude of a pulse supplied to a gate of a transistor constituting the signal processing unit. The pixel array and the level shift unit are arranged on a first semiconductor substrate, whereas the plurality of common output lines and the signal processing unit are arranged on a second semiconductor substrate.Type: ApplicationFiled: November 29, 2010Publication date: November 15, 2012Applicant: CANON KABUSHIKI KAISHAInventors: Tetsuya Itano, Kazuo Yamazaki, Nobuyuki Endo, Kyouhei Watanabe
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Publication number: 20120267690Abstract: The present invention relates to a solid-state image pickup device. The device includes a first substrate including a photoelectric conversion element and a transfer gate electrode configured to transfer charge from the photoelectric conversion element, a second substrate having a peripheral circuit portion including a circuit configured to read a signal based charge generated in the photoelectric conversion element, the first and second substrates being laminated. The device further includes a multilayer interconnect structure, disposed on the first substrate, including an aluminum interconnect and a multilayer interconnect structure, disposed on the second substrate, including a copper interconnect.Type: ApplicationFiled: December 22, 2010Publication date: October 25, 2012Applicant: CANON KABUSHIKI KAISHAInventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
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Publication number: 20120248293Abstract: A solid-state image pickup device includes a pixel region including photoelectric conversion units, FDs, and transfer transistors, reset transistors, amplifier transistors, and a reference voltage supply line used to supply reference voltages to the photoelectric conversion units. In the device, the pixel region and the reference voltage supply line are disposed on a first semiconductor substrate, and at least the reset transistors or the amplifier transistors are disposed on a second semiconductor substrate. Furthermore, power supply lines used to supply voltages to the reference voltage supply line are disposed on the second semiconductor substrate. The device further includes second electric connection units which electrically connect the reference voltage supply line to the power supply line. The first electric connection units are disposed in the pixel region whereas the second electric connection units are disposed outside the pixel region.Type: ApplicationFiled: December 13, 2010Publication date: October 4, 2012Applicant: CANON KABUSHIKI KAISHAInventors: Kazuo Yamazaki, Tetsuya Itano, Nobuyuki Endo, Kyouhei Watanabe
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Publication number: 20110301121Abstract: A nerve dysfunction repairing material including a hydrogel of a polysaccharide derivative that has, in a 0.5 wt % aqueous solution, a complex modulus of 1 to 1000 N/m2 and a loss factor of 0.01 to 2.0 as measured at an angular velocity of 10 rad/sec using a dynamic viscoelasticity measuring apparatus. The nerve dysfunction repairing material can be a hydrogel injectable through a syringe, has excellent retention in the body, and has a restorative effect on the function of damaged or degenerated nerves.Type: ApplicationFiled: September 18, 2009Publication date: December 8, 2011Applicants: UNIVERSITY NAGOYA NATIONAL UNIVERSITY CORPORATION, TEIJIN LIMITEDInventors: Nobuyuki Endo, Masaya Ito, Hiroaki Kaneko, Hitoshi Hirata, Michiro Yamamoto
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Patent number: 7985695Abstract: An oxide film formation method comprises steps of: generating a plasma from a gas mixture containing an inert gas and an oxidizing gas whose mixing ratio to the inert gas is higher than 0, and is 0.007 or lower; and forming an oxide film on a surface of a silicon substrate by using the plasma.Type: GrantFiled: September 25, 2008Date of Patent: July 26, 2011Assignee: Canon Kabushiki KaishaInventor: Nobuyuki Endo
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Publication number: 20110178184Abstract: A hydrogel comprising a polysaccharide, wherein amphiphilic side chains are bonded to the carboxyl groups of a polysaccharide with carboxyl groups on side chains, an inorganic ion other than calcium ion, and water, and a method for its preparation. The gel has high viscoelasticity, can be injected into the body using an instrument such as a syringe, and is useful for various biomedical materials.Type: ApplicationFiled: August 5, 2009Publication date: July 21, 2011Applicant: TEIJIN LIMITEDInventors: Hiroaki Kaneko, Masaya Ito, Nobuyuki Endo, Taishi Tanaka
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Publication number: 20110155893Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.Type: ApplicationFiled: December 21, 2010Publication date: June 30, 2011Applicant: CANON KABUSHIKI KAISHAInventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
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Publication number: 20110129505Abstract: The invention is a cellulose derivative wherein some of the carboxyl groups of the cellulose derivative carboxymethylcellulose are replaced with —CO—NH—X—CO—Y—Z, and a hydrogel of the same. In the formula, X is a C1-10 divalent hydrocarbon group, Y is a divalent group derived from polyalkylene oxide having oxygen atoms at both ends, and Z is a C1-24 hydrocarbon group or —CO—R4, where R4 is a C1-23 hydrocarbon group. The hydrogel has excellent viscoelasticity and can be injected into prescribed sites with injecting devices such as syringes, and it can thus be utilized as a medical gel or adhesion barrier.Type: ApplicationFiled: December 17, 2008Publication date: June 2, 2011Applicant: TEIJIN LIMITEDInventors: Hiroaki Kaneko, Nobuyuki Endo, Masaya Ito
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Publication number: 20110089513Abstract: A semiconductor device has an active region formed on a semiconductor substrate, a trench-type element isolation region formed on the semiconductor substrate, and a diffusion region in which fluorine is diffused that surrounds the element isolation region and is formed on the semiconductor substrate so as not to contact the active region.Type: ApplicationFiled: September 16, 2010Publication date: April 21, 2011Applicant: CANON KABUSHIKI KAISHAInventor: Nobuyuki Endo
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Publication number: 20100129452Abstract: The invention provides a cellulose derivative having a repeating unit of the formula below, a composition including the cellulose derivative and a phospholipid, a method for production thereof, and an adhesion barrier including the cellulose derivative or the composition. In the formula, R1, R2, and R3 are —H, —CH2—COOH, —CH2—COOX, or —CH2CO-phosphatidylethanolamine, and X is an alkali metal or an alkali earth metal. The degree of substitution of —CH2—COOH and —CH2—COOX is 0.3 to 2.0 in total, and the degree of substitution of —CH2CO-phosphatidylethanolamine is 0.001 to 0.05.Type: ApplicationFiled: February 6, 2008Publication date: May 27, 2010Applicant: TEIJIN LIMITEDInventors: Masaya Ito, Hiroaki Kaneko, Yukako Fukuhira, Nobuyuki Endo
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Publication number: 20090085171Abstract: An oxide film formation method comprises steps of: generating a plasma from a gas mixture containing an inert gas and an oxidizing gas whose mixing ratio to the inert gas is higher than 0, and is 0.007 or lower; and forming an oxide film on a surface of a silicon substrate by using the plasma.Type: ApplicationFiled: September 25, 2008Publication date: April 2, 2009Applicant: CANON KABUSHIKI KAISHAInventor: Nobuyuki Endo
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Patent number: 7490257Abstract: A clock distributor circuit is provided which works with power consumption reduced in semiconductor logic circuitry including clock synchronous circuits. The clock distributor circuit includes clock generation circuits generating gated clock signals in response to a clock enable signal to supply clock synchronous circuits with the generated clock signals. It is thus possible to reduce the power that would otherwise consumed by the toggling of the clock signal. A clock distribution method therefore is also provided.Type: GrantFiled: September 1, 2005Date of Patent: February 10, 2009Assignee: Oki Electric Industry Co., Ltd.Inventor: Nobuyuki Endo
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Patent number: 7202575Abstract: There is disclosed a semiconductor integrated circuit device capable of eliminating an influence of a power voltage drop generated in a circuit disposed in the semiconductor integrated circuit device to inhibit an operation defect or an operation speed decrease of the circuit. In a semiconductor integrated circuit device 10 including a power wiring 18 connected to a power supply (Vdd) via a power terminal 12, a ground wiring 20 connected to a ground (0 V) via a ground terminal 14, and a plurality of circuits 301 to 30f connected in parallel with one another between the power wiring 18 and the ground wiring 20, a negative power terminal 16 connected to a negative power supply (?Vdd) is disposed, and a current source 22 is disposed as a current generating section between the negative power terminal 16 and a node Gf on a ground wiring 20 side of the f-th circuit 30f disposed in a region most distant from the ground.Type: GrantFiled: February 25, 2004Date of Patent: April 10, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Nobuyuki Endo
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Patent number: 7200706Abstract: A semiconductor integrated circuit includes a local memory permitting high-speed access. The local memory has at least first and second ports. The first port of the local memory is connected to a CPU by a first bus and the second port of the local memory is connected to an access control unit by a second bus. An external device is connected to the access control unit. When the CPU and/or the external device accesses the local memory, the CPU sends a control signal and data to the first port (CPU-access port) of the local memory via the first bus, and the access control unit sends another control signal and data to the second port (external-device-access port) of the local memory via the second bus. The local memory then executes data writing or reading based on the control signal(s) and data thus introduced to the access port(s). The external device can access the local memory via the access control unit to transfer data at high speed to and from the local memory.Type: GrantFiled: April 22, 2004Date of Patent: April 3, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Nobuyuki Endo
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Patent number: 7065686Abstract: A dual port RAM includes an any-time readable/writable memory block in which an access can be made to the same storage area from independent first and second ports. In addition, the RAM includes a first test circuit for performing a test to the storage area of the memory block via the first port on the basis of a first clock signal, and a second test circuit for performing a test to the storage area of the memory block via the second port on the basis of a second clock signal. A control circuit of the RAM causes the first and second test circuits to test the memory block in an alternating manner.Type: GrantFiled: June 19, 2002Date of Patent: June 20, 2006Assignee: Oki Electric Industry Co., Ltd.Inventors: Nobuyuki Endo, Yuji Fujiki, Hiroki Goko, Fumihiro Wajima, Junichi Tamura, Ali Elhadri
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Publication number: 20060049863Abstract: A clock distributor circuit is provided which works with power consumption reduced in semiconductor logic circuitry including clock synchronous circuits. The clock distributor circuit includes clock generation circuits generating gated clock signals in response to a clock enable signal to supply clock synchronous circuits with the generated clock signals. It is thus possible to reduce the power that would otherwise consumed by the toggling of the clock signal. A clock distribution method therefor is also provided.Type: ApplicationFiled: September 1, 2005Publication date: March 9, 2006Inventor: Nobuyuki Endo