Patents by Inventor Nobuyuki Fujii

Nobuyuki Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240141471
    Abstract: A method of forming an Al—Zn—Si—Mg alloy coating on a steel strip includes dipping steel strip into a bath of molten Al—Zn—Si—Mg alloy and forming a coating of the alloy on exposed surfaces of the steel strip. The method also includes controlling conditions in the molten coating bath and downstream of the coating bath so that there is a uniform Al/Zn ratio across the surface of the coating formed on the steel strip. An Al—Zn—Mg—Si coated steel strip includes a uniform Al/Zn ratio on the surface or the outermost 1-2 ?m of the Al—Zn—Si—Mg alloy coating.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 2, 2024
    Applicants: Bluescope Steel Limited, Nippon Steel Corporation, Nippon Steel Coated Sheet Corporation
    Inventors: Wayne Andrew RENSHAW, Cat TU, Joe WILLIAMS, Jason HODGES, Shiro FUJII, Nobuyuki SHIMODA, Shuichi KONDO, Takashi HIRASAWA
  • Publication number: 20240072471
    Abstract: A connector (10), into and from which a connection object (70) is insertable and removable, includes an insulator (20) including an insertion portion (23) in which a connection object (70) can be inserted and a first contact (30) mounted on the insulator (20). The first contact (30) includes a contact piece (34) and a resiliently deformable resilient portion (33). The contact piece (34) includes a contact portion (35) configured to be connected to a signal line (73) of the connection object (70) in a fully inserted state where the connection object (70) is fully inserted in the insertion portion (23) and a removing portion (36) located closer to an insertion opening (23a) of the insertion portion (23) than the contact portion (35). The removing portion (36) is configured to be connected to the signal line (73) in a partially inserted state where the connection object (70) is partially inserted in the insertion portion (23).
    Type: Application
    Filed: January 12, 2022
    Publication date: February 29, 2024
    Inventors: Yousuke MANBA, Yoshiharu FUJII, Nobuyuki NAKAJIMA
  • Patent number: 8975786
    Abstract: When portable electronic equipment drops, CPU stops power supply to a prescribed unit. A prescribed unit is a unit that is not necessary for the continuous operation of the portable electronic equipment. When the portable electronic equipment collides with the floor or the ground, the battery terminal may be momentarily detached from the connector. In this case, instantaneous voltage drop or momentary power failure may occur. Power supply to a prescribed unit is stopped while power supply to CPU and RAM is continued. Therefore, power supply to CPU and RAM can be continued with electric charge stored in a capacitor inside the portable electronic equipment.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: March 10, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Nobuyuki Fujii
  • Patent number: 8658354
    Abstract: A method of immunoassay of H5 subtype influenza A virus by which the virus can be accurately assayed even in cases where a certain level of mutation has occurred in the H5 subtype influenza A virus, and a kit therefor, and a novel anti-H5 subtype influenza A virus monoclonal antibody which can be used for the immunoassay are disclosed. The antibody or an antigen-binding fragment thereof of the present invention undergoes antigen-antibody reaction with hemagglutinin of H5 subtype influenza A virus, and the corresponding epitope of the antibody or an antigen-binding fragment thereof is located in a region other than the receptor subdomain (excluding C-terminal region thereof consisting of 11 amino acids), which antibody or an antigen-binding fragment thereof does not have neutralizing activity against the influenza A virus.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: February 25, 2014
    Assignees: National University Corporation Hokkaido University, Fujirebio Inc.
    Inventors: Hiroshi Kida, Yoshihiro Sakoda, Eiji Miyagawa, Nobuyuki Fujii, Yoshiaki Uchida, Takashi Shirakawa, Hiroyuki Kogaki
  • Publication number: 20130109010
    Abstract: A novel means by which HCMV infection can be detected with a high sensitivity and whose practicality is high is disclosed. The present inventors synthesized as many as 15 kinds of HCMV proteins in their full length forms, and intensively studied their reactivities with sera from HCMV-infected patients to find that all the infected patients can be detected without fail when using the pp28 full length protein as an antigen. The pp28 full length protein can be synthesized and purified as a recombinant protein in a large scale by using Escherichia coli, and can be commercially used as an antigen for HCMV tests.
    Type: Application
    Filed: July 5, 2011
    Publication date: May 2, 2013
    Applicant: FUJIREBIO INC.
    Inventors: Nobuyuki Fujii, Hideo Honda, Yoshiaki Uchida, Kazuya Omi
  • Publication number: 20120133218
    Abstract: When portable electronic equipment drops, CPU stops power supply to a prescribed unit. A prescribed unit is a unit that is not necessary for the continuous operation of the portable electronic equipment. When the portable electronic equipment collides with the floor or the ground, the battery terminal may be momentarily detached from the connector. In this case, instantaneous voltage drop or momentary power failure may occur. Power supply to a prescribed unit is stopped while power supply to CPU and RAM is continued. Therefore, power supply to CPU and RAM can be continued with electric charge stored in a capacitor inside the portable electronic equipment.
    Type: Application
    Filed: May 20, 2011
    Publication date: May 31, 2012
    Inventor: Nobuyuki FUJII
  • Publication number: 20110065095
    Abstract: A method of immunoassay of H5 subtype influenza A virus by which the virus can be accurately assayed even in cases where a certain level of mutation has occurred in the H5 subtype influenza A virus, and a kit therefor, and a novel anti-H5 subtype influenza A virus monoclonal antibody which can be used for the immunoassay are disclosed. The antibody or an antigen-binding fragment thereof of the present invention undergoes antigen-antibody reaction with hemagglutinin of H5 subtype influenza A virus, and the corresponding epitope of the antibody or an antigen-binding fragment thereof is located in a region other than the receptor subdomain (excluding C-terminal region thereof consisting of 11 amino acids), which antibody or an antigen-binding fragment thereof does not have neutralizing activity against the influenza A virus.
    Type: Application
    Filed: March 26, 2009
    Publication date: March 17, 2011
    Applicants: National University Corporation Hokkaido Univ, Fujirebio Inc.
    Inventors: Hiroshi Kida, Yoshihiro Sakoda, Eiji Miyagawa, Nobuyuki Fujii, Yoshiaki Uchida, Takashi Shirakawa, Hiroyuki Kogaki
  • Publication number: 20080254440
    Abstract: A monoclonal antibody which specifically recognizes SARS virus is provided, and an immunoassay, immunoassay reagent and immunoassay device for detecting the SARS virus using the monoclonal antibody are disclosed. The monoclonal antibody according to the present invention is a monoclonal antibody against a nucleoprotein of a corona virus causing severe acute respiratory syndrome (SARS).
    Type: Application
    Filed: October 29, 2004
    Publication date: October 16, 2008
    Inventors: Yoshiaki Uchida, Nobuyuki Fujii, Yoshihiro Kurano, Masahisa Okada, Hiroyuki Kogaki, Yasuji Kido, Kazushige Miyake
  • Patent number: 7030681
    Abstract: Well bias voltages are generated in accordance with a logic power supply voltage and a memory power supply voltage. The transistor included in a control circuit in a memory core is constituted of a logic transistor manufactured through the same manufacturing steps as those for the transistors of a logic formed on the same semiconductor substrate. Well bias voltages (VBB, VPP) are applied to a back gate of this logic transistor. A memory integrated with a logic on a common semiconductor substrate is provided which allows a transistor of a control circuit therein to be manufactured through the same manufacturing process as that of the logic and allows reduction of current consumption.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: April 18, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Akira Yamazaki, Fukashi Morishita, Yasuhiko Taito, Nobuyuki Fujii, Mako Okamoto
  • Publication number: 20060015795
    Abstract: An audio data processor includes a packet receiver for receiving audio data packets and a coded data extractor for extracting coded data from the received packets. When an error detector detects a receiving error of a packet in the packet receiver, a data interpolator generates interpolation coded data on the basis of coded data of a packet normally received immediately before the missing packet, and interpolates coded data of the missing packet by the interpolation coded data.
    Type: Application
    Filed: July 1, 2005
    Publication date: January 19, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Manabu Miura, Nobuyuki Fujii, Yoshifumi Hanamoto, Yoshiyuki Osako
  • Patent number: 6781431
    Abstract: The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: August 24, 2004
    Assignees: Rensas Technology Corp., Mitsubishi Electric Engineering Company Limited
    Inventors: Yasuhiko Taito, Akira Yamazaki, Fukashi Morishita, Nobuyuki Fujii, Mihoko Akiyama, Mako Okamoto
  • Patent number: 6777707
    Abstract: A VDC circuit that supplies an internal voltage VDD1 to an internal circuit in a normal operation forces a transistor off in a burn-in test mode through input of a test signal to suppress supply of an external power supply voltage VDDH to a node. In a burn-in test mode, an external power supply voltage lower than external power supply voltage VDDH and higher than internal voltage VDD1 is supplied from an external pad.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: August 17, 2004
    Assignees: Renesas Technology Corp., Mitsubishi Electric Engineering Company Limited
    Inventors: Mihoko Akiyama, Akira Yamazaki, Fukashi Morishita, Yasuhiko Taito, Nobuyuki Fujii, Mako Okamoto
  • Patent number: 6768354
    Abstract: With power-on detection circuits provided for a plurality of power supply voltages, a main power-on detection signal is maintained at the active state to reset an internal node while at least one of the power-on detection signals is active. In a multi-power semiconductor integrated circuit device, current consumption at the time of power-up is reduced.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: July 27, 2004
    Assignees: Renesas Technology Corp., Mitsubishi Electric Engineering Company Limited
    Inventors: Akira Yamazaki, Fukashi Morishita, Yasuhiko Taito, Nobuyuki Fujii, Mihoko Akiyama, Mako Kobayashi
  • Patent number: 6700434
    Abstract: Oscillation outputs which are different for respective detector signals output from a first detector circuit and a second detector circuit, are obtained from a first ring oscillator and a second ring oscillator respectively corresponding to the detector circuits. A selector selects and outputs one of the oscillation outputs. Accordingly, it is sufficient to provide only one pump circuit in a circuit producing a substrate bias voltage.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: March 2, 2004
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.
    Inventors: Nobuyuki Fujii, Fukashi Morishita, Mihoko Akiyama, Akira Yamazaki, Mako Kobayashi, Yasuhiko Taito
  • Publication number: 20040018534
    Abstract: Disclosed are a fused DNA sequence which comprises a DNA sequence of a heat-resistant protein, fused directly or indirectly to a DNA sequence coding a selected protein or peptide, a fused protein expressed from the fused DNA sequence, and a method for expressing the fused protein.
    Type: Application
    Filed: June 10, 2003
    Publication date: January 29, 2004
    Applicant: FUJIREBIO INC.
    Inventors: Eiichi Ueno, Nobuyuki Fujii, Masahisa Okada
  • Patent number: 6665217
    Abstract: A tuning control circuit includes fuse devices each shifting from a conductive state to an interrupted state in response to a program input from the outside, and signal driving circuits for driving the signal levels of tuning control signals in accordance with the states of the fuse devices. A reference voltage generating circuit generates a reference voltage corresponding to a reference value of a memory array voltage of a semiconductor memory device according to the invention in accordance with an electrical resistance value which is finely adjusted in response to the tuning control signals.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: December 16, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fukashi Morishita, Yasuhiko Taito, Akira Yamazaki, Mako Okamoto, Nobuyuki Fujii
  • Patent number: 6614270
    Abstract: In a detector included in a VPP generating circuit in a DRAM, an external power supply potential is applied to the gate of an N-channel MOS transistor for regulating a through current of an inverter for outputting an inversion signal of an output signal of a comparator. Since a drain-source voltage of the N-channel MOS transistor can be set to be lower than a threshold voltage Vthn of the N-channel MOS transistor, an operation margin of the detector under conditions of a low voltage and a low temperature is made wider as compared with a conventional technique.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: September 2, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company Limited
    Inventors: Mako Okamoto, Yasuhiko Taito, Fukashi Morishita, Akira Yamazaki, Mihoko Akiyama, Nobuyuki Fujii
  • Patent number: 6602689
    Abstract: Disclosed are a fused DNA sequence which comprises a DNA sequence of a heat-resistant protein, fused directly or indirectly to a DNA sequence coding a selected protein or peptide, a fused protein expressed from the fused DNA sequence, and a method for expressing the fused protein.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: August 5, 2003
    Assignee: Fujirebio Inc.
    Inventors: Eiichi Ueno, Nobuyuki Fujii, Masahisa Okada
  • Patent number: 6593642
    Abstract: A DRAM is provided at a portion relating to generation of a boosted potential with a filter circuit located between a detector circuit and a ring oscillator for removing a pulse-like change in level from an output signal of the detector circuit. Accordingly, temporary stop of the charge pump circuit can be prevented even when the boosted potential exceeds in a pulse-like manner the reference potential at the vicinity of the output node of the charge pump circuit, and the boosted potential can be rapidly restored to the reference potential.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: July 15, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mako Okamoto, Yasuhiko Taito, Fukashi Morishita, Akira Yamazaki, Nobuyuki Fujii
  • Publication number: 20030117204
    Abstract: The clock generating circuit includes: an oscillator generating a reference clock signal; an EX-OR gate connected in a ring configuration; and first and second D latch circuits. The EX-OR gate inverts a clock signal to provide the inverted clock signal to the first D latch circuit when an activating signal is at H level. In this case, the clock signal is a clock signal having a clock cycle period of twice that of the reference clock signal. The EX-OR gate provides the clock signal direct to the first D latch circuit when the activating signal is set to L level. In this case, level transition of the clock signal is ceased. Hence, generation of a glitch in the clock signal is prevented from occurring.
    Type: Application
    Filed: January 23, 2003
    Publication date: June 26, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yasuhiko Taito, Akira Yamazaki, Fukashi Morishita, Nobuyuki Fujii, Mihoko Akiyama, Mako Okamoto