Patents by Inventor Nobuyuki Mise
Nobuyuki Mise has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120520Abstract: A decrease in output power due to a foreign matter present on a base at the time of forming a thin film solid electrolyte layer is limited, and an increase in yield even when an area of a fuel battery cell is increased, is obtained. The fuel battery cell has a membrane electrode assembly including a lower electrode layer, first and second solid electrolyte layers, and an upper electrode layer formed on a support substrate. An interface between the first and second solid electrolyte layers is flat as compared with an interface between the lower electrode layer and the solid electrolyte layer, and the second solid electrolyte layer has a thickness at which a leakage current between the first solid electrolyte layer and the second solid electrolyte layer is less than an allowable value even when an output voltage of the fuel battery cell is generated.Type: ApplicationFiled: March 31, 2021Publication date: April 11, 2024Inventors: Yoshitaka SASAGO, Noriyuki SAKUMA, Natsuki YOKOYAMA, Koji FUJISAKI, Nobuyuki MISE, Aritoshi SUGIMOTO
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Patent number: 11855318Abstract: The present invention aims to provide a fuel battery system improved in reliability by accurately detecting when a fuel electrode gas or an air electrode gas has leaked. A fuel battery cell according to the present invention includes a first electrode, an electrolyte membrane, and a second electrode which are layered on a support substrate. Further, at least any one of the first electrode, the electrolyte membrane, and the second electrode is electrically isolated by an insulating member to form a first region and a second region. The insulating member is disposed at a position where the insulating member does not overlap with an opening portion of the support substrate (refer to FIG. 3).Type: GrantFiled: April 26, 2019Date of Patent: December 26, 2023Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Munenori Degawa, Noriyuki Sakuma, Yoshitaka Sasago, Aritoshi Sugimoto, Nobuyuki Mise, Takashi Tsutsumi
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Publication number: 20230127271Abstract: A fuel cell 1 includes a silicon substrate 2, a porous support material layer 5, a plurality of holes 60 or columns 40, and a stacked body. The stacked body includes an upper electrode layer 10, a solid electrolyte layer 100 and a lower electrode layer 20. The upper electrode layer 10 is also formed on a surface parallel to a main surface of the silicon substrate 2 in a manner of being continuous to the upper electrode layer 10 formed in the plurality of holes 60 or columns 40, or the lower electrode layer 20 is also formed on a surface parallel to the main surface of the silicon substrate 2 in a manner of being continuous to the lower electrode layer 20 formed in the plurality of holes 60 or columns 40. The stacked body is supported by the porous support material layer 5 in at least upper end portions and lower end portions of the plurality of holes 60 or columns 40.Type: ApplicationFiled: May 13, 2020Publication date: April 27, 2023Inventors: Yoshitaka SASAGO, Noriyuki SAKUMA, Natsuki YOKOYAMA, Atsushi UNEMOTO, Takashi TSUTSUMI, Aritoshi SUGIMOTO, Toru ARAMAKI, Nobuyuki MISE
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Patent number: 11417892Abstract: Provided is a highly reliable fuel cell that improves power generation efficiency of the fuel cell and that is less likely to cause damage to an electrode and an electrolyte film. The fuel cell includes a support substrate (2, 3) having a region in which a support portion having a mesh-like shape in a plan view is provided, a first electrode 4 on the support substrate, an electrolyte film 5 on the first electrode, and a second electrode 6 on the electrolyte film. The first electrode includes a first thin film electrode 4A formed in a manner of covering at least the region, and a first mesh-like electrode 4B connected to the first thin film electrode and provided corresponding to the support portion. The first mesh-like electrode 4B has a film thickness larger than that of the first thin film electrode and has a mesh-like shape in a plan view.Type: GrantFiled: October 12, 2018Date of Patent: August 16, 2022Assignee: Hitachi High-Tech CorporationInventors: Noriyuki Sakuma, Yoshitaka Sasago, Aritoshi Sugimoto, Nobuyuki Mise, Seiichi Watanabe
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Publication number: 20220181658Abstract: The present invention aims to provide a fuel battery system improved in reliability by accurately detecting when a fuel electrode gas or an air electrode gas has leaked. A fuel battery cell according to the present invention includes a first electrode, an electrolyte membrane, and a second electrode which are layered on a support substrate. Further, at least any one of the first electrode, the electrolyte membrane, and the second electrode is electrically isolated by an insulating member to form a first region and a second region. The insulating member is disposed at a position where the insulating member does not overlap with an opening portion of the support substrate (refer to FIG. 3).Type: ApplicationFiled: April 26, 2019Publication date: June 9, 2022Applicant: HITACHI HIGH-TECH CORPORATIONInventors: Munenori DEGAWA, Noriyuki SAKUMA, Yoshitaka SASAGO, Aritoshi SUGIMOTO, Nobuyuki MISE, Takashi TSUTSUMI
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Publication number: 20210408556Abstract: Provided is a highly reliable fuel cell that improves power generation efficiency of the fuel cell and that is less likely to cause damage to an electrode and an electrolyte film. The fuel cell includes a support substrate (2, 3) having a region in which a support portion having a mesh-like shape in a plan view is provided, a first electrode 4 on the support substrate, an electrolyte film 5 on the first electrode, and a second electrode 6 on the electrolyte film. The first electrode includes a first thin film electrode 4A formed in a manner of covering at least the region, and a first mesh-like electrode 4B connected to the first thin film electrode and provided corresponding to the support portion. The first mesh-like electrode 4B has a film thickness larger than that of the first thin film electrode and has a mesh-like shape in a plan view.Type: ApplicationFiled: October 12, 2018Publication date: December 30, 2021Inventors: Noriyuki SAKUMA, Yoshitaka SASAGO, Aritoshi SUGIMOTO, Nobuyuki MISE, Seiichi WATANABE
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Patent number: 8698249Abstract: A CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising: a gate electrode of the n-type MOSFET having a first insulation layer composed of a high-k material, and a first metal layer provided on the first insulation layer and composed of a metal material; and a gate electrode of the p-type MOSFET having a second insulation layer composed of a high-k material, and a second metal layer provided on the second insulation layer and composed of a metal material, wherein the first insulation layer and the second insulation layer are composed of the different high-k materials, and the first metal layer and the second metal layer are composed of the same metal material.Type: GrantFiled: August 6, 2012Date of Patent: April 15, 2014Assignee: Renesas Electronics CorporationInventors: Nobuyuki Mise, Takahisa Eimori
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Patent number: 8466053Abstract: A gate insulating film is formed on a substrate. Next, a gate electrode film is formed on the gate insulating film. A mask film is formed on a portion of the gate electrode film. The gate electrode film is selectively removed by etching using the mask film as a mask. A gate sidewall film is formed so as to be in contact with the lateral surfaces of the mask film and the gate electrode film. The mask film is formed of a laminated film in which at least a first film, a second film and a third film are laminated in this order. The second film has a higher etching selectivity ratio than that of the third film with respect to the gate sidewall film. The third film has a higher etching selectivity ratio than that of the second film with respect to the gate electrode film.Type: GrantFiled: March 29, 2011Date of Patent: June 18, 2013Assignee: Renesas Electronics CorporationInventors: Takeo Matsuki, Nobuyuki Mise
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Patent number: 8404603Abstract: A method of manufacturing a semiconductor device. In the method, an aluminum-containing insulation film is formed on an electrode film of a substrate by alternately repeating a process of supplying an aluminum precursor into a processing chamber in which the substrate is accommodated and exhausting the aluminum precursor from the processing chamber and a process of supplying an oxidizing or nitriding precursor into the processing chamber and exhausting the oxidizing or nitriding precursor from the processing chamber; and a high permittivity insulation film different from the aluminum-containing insulation film is formed on the aluminum-containing insulation film by alternately repeating a process of supplying a precursor into the processing chamber and exhausting the precursor from the processing chamber and a process of supplying an oxidizing precursor into the processing chamber and exhausting the oxidizing precursor from the processing chamber. In addition, heat treatment is performed on the substrate.Type: GrantFiled: June 28, 2010Date of Patent: March 26, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Arito Ogawa, Sadayoshi Horii, Taketoshi Sato, Hideharu Itatani, Nobuyuki Mise, Osamu Tonomura
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Publication number: 20130034953Abstract: A CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising: a gate electrode of the n-type MOSFET having a first insulation layer composed of a high-k material, and a first metal layer provided on the first insulation layer and composed of a metal material; and a gate electrode of the p-type MOSFET having a second insulation layer composed of a high-k material, and a second metal layer provided on the second insulation layer and composed of a metal material, wherein the first insulation layer and the second insulation layer are composed of the different high-k materials, and the first metal layer and the second metal layer are composed of the same metal material.Type: ApplicationFiled: August 6, 2012Publication date: February 7, 2013Inventors: Nobuyuki Mise, Takahisa Eimori
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Patent number: 8288221Abstract: A base insulating film containing hafnium and oxygen is formed on a silicon oxide (SiO2) film formed on a main surface of a substrate. Subsequently, a metal thin film thinner than the base insulating film and made of only a metal element is formed on the base insulating film, and a protective film having humidity resistance and oxidation resistance is formed on the metal thin film. Then, by diffusing the entire metal element of the metal thin film into the base insulating film in a state of having the protective film, a mixed film (high dielectric constant film) thicker than the silicon oxide film and having a higher dielectric constant than silicon oxide and containing hafnium and oxygen of the base insulating film and the metal element of the metal thin film is formed on the silicon oxide film.Type: GrantFiled: August 7, 2009Date of Patent: October 16, 2012Assignee: Renesas Electronics CorporationInventors: Takahisa Eimori, Nobuyuki Mise
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Publication number: 20110241087Abstract: A gate insulating film is formed on a substrate. Next, a gate electrode film is formed on the gate insulating film. A mask film is formed on a portion of the gate electrode film. The gate electrode film is selectively removed by etching using the mask film as a mask. A gate sidewall film is formed so as to be in contact with the lateral surfaces of the mask film and the gate electrode film. The mask film is formed of a laminated film in which at least a first film, a second film and a third film are laminated in this order. The second film has a higher etching selectivity ratio than that of the third film with respect to the gate sidewall film. The third film has a higher etching selectivity ratio than that of the second film with respect to the gate electrode film.Type: ApplicationFiled: March 29, 2011Publication date: October 6, 2011Inventors: Takeo MATSUKI, Nobuyuki MISE
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Patent number: 7968396Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.Type: GrantFiled: November 25, 2009Date of Patent: June 28, 2011Assignees: Seiko Epson Corporation, Renesas Technology CorporationInventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
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Patent number: 7947560Abstract: A method for forming silicide includes the steps of: forming a nickel film on a silicon layer (or a silicon substrate); introducing nitrogen into at least one of the nickel film and the interface between the nickel film and the silicon layer (or the silicon substrate); and after the introduction of the nitrogen, applying heat treatment to the nickel film and the silicon layer (or the silicon substrate) under predetermined conditions to form a nickel disilicide layer.Type: GrantFiled: February 21, 2007Date of Patent: May 24, 2011Assignees: Seiko Epson Corporation, Renesas Technology CorporationInventors: Yukimune Watanabe, Nobuyuki Mise, Shinji Migita
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Publication number: 20110003482Abstract: Provided is a method of manufacturing a semiconductor device. In the method, an aluminium-containing insulation film is formed on an electrode film of a substrate by alternately repeating a process of supplying an aluminium precursor into a processing chamber in which the substrate is accommodated and exhausting the aluminium precursor from the processing chamber and a process of supplying an oxidizing or nitriding precursor into the processing chamber and exhausting the oxidizing or nitriding precursor from the processing chamber; and a high permittivity insulation film different from the aluminium-containing insulation film is formed on the aluminium-containing insulation film by alternately repeating a process of supplying a precursor into the processing chamber and exhausting the precursor from the processing chamber and a process of supplying an oxidizing precursor into the processing chamber and exhausting the oxidizing precursor from the processing chamber.Type: ApplicationFiled: June 28, 2010Publication date: January 6, 2011Applicant: HITACHI-KOKUSAI ELECTRIC INC.Inventors: Arito Ogawa, Sadayoshi Horii, Taketoshi SATO, Hideharu Itatani, Nobuyuki MISE, Osamu Tonomura
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Patent number: 7863127Abstract: After forming a first gate electrode and a second gate electrode on a semiconductor substrate, a silicon oxide film is formed to cover an n-channel MISFET forming region, and a p-channel MISFET forming region is exposed. Subsequently, after a first element supply film made of, for example, an aluminum oxide film is formed on the whole surface of the semiconductor substrate, a heat treatment is performed. By this means, a high-concentration HfAlO film and a low-concentration HfAlO film are formed by diffusing aluminum into the first insulating film just below the second gate electrode. Thereafter, by using a magnesium oxide film as a second element supply film, magnesium is diffused into the first insulating film just below the first gate electrode, thereby forming a high-concentration HfMgO film and a low-concentration HfMgO film.Type: GrantFiled: May 22, 2009Date of Patent: January 4, 2011Assignee: Renesas Electronics CorporationInventors: Nobuyuki Mise, Tetsu Morooka
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Publication number: 20100258878Abstract: A CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising: a gate electrode of the n-type MOSFET having a first insulation layer composed of a high-k material, and a first metal layer provided on the first insulation layer and composed of a metal material; and a gate electrode of the p-type MOSFET having a second insulation layer composed of a high-k material, and a second metal layer provided on the second insulation layer and composed of a metal material, wherein the first insulation layer and the second insulation layer are composed of the different high-k materials, and the first metal layer and the second metal layer are composed of the same metal material.Type: ApplicationFiled: November 26, 2008Publication date: October 14, 2010Inventors: Nobuyuki Mise, Takahisa Eimori
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Publication number: 20100072551Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.Type: ApplicationFiled: November 25, 2009Publication date: March 25, 2010Applicants: SEIKO EPSON CORPORATION, RENESAS TECHNOLOGY CORPORATIONInventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
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Patent number: 7671426Abstract: In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the central side in the gate-length direction, and including more nitrogen at the upper side than at the lower side in the film thickness direction. The reliability and characteristics of a MIS transistor using a gate insulator including a high-k (high dielectric constant) film is enhanced.Type: GrantFiled: February 10, 2009Date of Patent: March 2, 2010Assignee: Renesas Technology Corp.Inventors: Nobuyuki Mise, Akira Toriumi
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Publication number: 20100038729Abstract: A base insulating film containing hafnium and oxygen is formed on a silicon oxide (SiO2) film formed on a main surface of a substrate. Subsequently, a metal thin film thinner than the base insulating film and made of only a metal element is formed on the base insulating film, and a protective film having humidity resistance and oxidation resistance is formed on the metal thin film. Then, by diffusing the entire metal element of the metal thin film into the base insulating film in a state of having the protective film, a mixed film (high dielectric constant film) thicker than the silicon oxide film and having a higher dielectric constant than silicon oxide and containing hafnium and oxygen of the base insulating film and the metal element of the metal thin film is formed on the silicon oxide film.Type: ApplicationFiled: August 7, 2009Publication date: February 18, 2010Inventors: Takahisa EIMORI, Nobuyuki Mise