Patents by Inventor Nobuyuki Ohtsuka

Nobuyuki Ohtsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090321937
    Abstract: A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess.
    Type: Application
    Filed: April 29, 2009
    Publication date: December 31, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Masaki HANEDA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Michie SUNAYAMA, Takahiro TABIRA
  • Publication number: 20090146309
    Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.
    Type: Application
    Filed: November 20, 2008
    Publication date: June 11, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hiroshi KUDO, Nobuyuki OHTSUKA, Masaki HANEDA, Tamotsu OWADA
  • Publication number: 20090121355
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Application
    Filed: November 10, 2008
    Publication date: May 14, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Masaki HANEDA, Michie SUNAYAMA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Takahiro TABIRA
  • Patent number: 7507666
    Abstract: An insulating film having a concave portion is formed on a semiconductor substrate. The inner surface of the concave portion and the upper surface of the insulating film are covered with an auxiliary film made of Cu alloy containing a first metal element other than Cu. A conductive member containing Cu as a main composition is deposited on the auxiliary film, the conductive member being embedded in the concave portion. Heat treatment is performed in an atmosphere containing P compound, Si compound or B compound. With this method, a content of element other than Cu in the conductive member can be reduced and a resistivity can be lowered.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: March 24, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Yoshiyuki Nakao, Hideki Kitada, Nobuyuki Ohtsuka, Noriyoshi Shimizu
  • Patent number: 7507659
    Abstract: A method for fabricating a semiconductor device has forming an opening defined by an inner wall surface in an insulation film, covering said inner wall surface with a Cu—Mn alloy layer, depositing a first Cu layer over said Cu—Mn alloy layer without exposing said Cu—Mn alloy layer to the air, depositing a second Cu layer over said first Cu layer and filling said opening with said second Cu layer, and forming a barrier layer over said inner wall surface as a result of a reaction between Mn in said Cu—Mn alloy layer and said insulation film.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: March 24, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Nobuyuki Ohtsuka, Noriyoshi Shimizu, Yoshiyuki Nakao
  • Publication number: 20080286960
    Abstract: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.
    Type: Application
    Filed: July 11, 2008
    Publication date: November 20, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Noriyoshi Shimizu, Nobuyuki Ohtsuka, Hideki Kitada, Yoshiyuki Nakao
  • Patent number: 7413977
    Abstract: A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. Then a first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. Then conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. Then the semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: August 19, 2008
    Assignee: Fujitsu Limited
    Inventors: Noriyoshi Shimizu, Nobuyuki Ohtsuka, Hideki Kitada, Yoshiyuki Nakao
  • Publication number: 20080113506
    Abstract: A method for fabricating a semiconductor device has forming an opening defined by an inner wall surface in an insulation film, covering said inner wall surface with a Cu—Mn alloy layer, depositing a first Cu layer over said Cu—Mn alloy layer without exposing said Cu—Mn alloy layer to the air, depositing a second Cu layer over said first Cu layer and filling said opening with said second Cu layer, and forming a barrier layer over said inner wall surface as a result of a reaction between Mn in said Cu—Mn alloy layer and said insulation film.
    Type: Application
    Filed: November 13, 2007
    Publication date: May 15, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Nobuyuki OHTSUKA, Noriyoshi SHIMIZU, Yoshiyuki NAKAO
  • Patent number: 7279790
    Abstract: A multilayer interconnection structure that offers a fast semiconductor operation is realized by employing copper wiring, electro migration of which is prevented from occurring by providing a via plug that includes a layer of a high melting-point metal, such as tungsten.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: October 9, 2007
    Assignee: Fujitsu Limited
    Inventors: Hideki Kitada, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Takayuki Ohba
  • Publication number: 20070173055
    Abstract: A method for fabricating a semiconductor device includes the steps of forming an opening defined by an inner wall surface in an insulation film, forming a Cu—Mn alloy layer in the opening, depositing a Cu layer on the Cu—Mn alloy layer and filling the opening with the Cu layer, and forming a barrier layer as a result of reaction between Mn atoms in the Cu—Mn alloy layer and the insulation film, wherein the step of forming the barrier layer is conducted by exposing the Cu layer to an ambient that forms a gaseous reaction product when reacted with Mn.
    Type: Application
    Filed: January 18, 2007
    Publication date: July 26, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Nobuyuki Ohtsuka, Noriyoshi Shimizu, Yoshiyuki Nakao, Hisaya Sakai
  • Publication number: 20070134899
    Abstract: (a) A recess is formed through an insulating film formed over a semiconductor substrate. (b) After the recess is formed, a temperature of the substrate is raised to 300° C. or higher at a temperature rising rate of 10° C./s or slower and a first degassing process is executed. (c) After the first degassing process, a conductive film is deposited on the insulating film, the conductive film being embedded in the recess. (d) The deposited conductive film is polished until the insulating film is exposed. It is possible to suppress occurrence of defects during CMP to be performed after a conductive member is deposited on the surface of the insulating film having a recess formed therethrough.
    Type: Application
    Filed: March 3, 2006
    Publication date: June 14, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi Kanki, Nobuyuki Ohtsuka, Hisaya Sakai, Noriyoshi Shimizu
  • Patent number: 7199044
    Abstract: In a method for manufacturing a semiconductor device, an insulating film having pores is formed on a substrate, and an opening is formed in the insulating film. Thereafter, a material gas supplying Si or C is supplied to the insulating film. Thereby, deficient elements, such as Si or C, are supplied to the insulating film. Thereafter, the opening, including a barrier metal, is filled with a conductive member to form a wiring structure.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: April 3, 2007
    Assignee: Fujitsu Limited
    Inventors: Nobuyuki Ohtsuka, Akira Furuya, Shinichi Ogawa, Hiroshi Okamura
  • Publication number: 20070049024
    Abstract: An insulating film having a concave portion is formed on a semiconductor substrate. The inner surface of the concave portion and the upper surface of the insulating film are covered with an auxiliary film made of Cu alloy containing a first metal element other than Cu. A conductive member containing Cu as a main composition is deposited on the auxiliary film, the conductive member being embedded in the concave portion. Heat treatment is performed in an atmosphere containing P compound, Si compound or B compound. With this method, a content of element other than Cu in the conductive member can be reduced and a resistivity can be lowered.
    Type: Application
    Filed: December 6, 2005
    Publication date: March 1, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiyuki Nakao, Hideki Kitada, Nobuyuki Ohtsuka, Noriyoshi Shimizu
  • Publication number: 20070045851
    Abstract: An interlayer insulating film having a concave portion is formed on a semiconductor substrate. A tight adhesion film is formed on the inner surface of the concave portion and the upper surface of the insulating film. The surface of the adhesion layer is covered with an auxiliary film made of Cu alloy containing a first metal element. A conductive member containing a second metal element other than the first metal element is embedded in the concave portion, and deposited on the auxiliary film. Heat treatment is performed to make atoms of the first metal element in the auxiliary film segregate on the inner surface of the concave portion. The adhesion layer contains an element for enhancing tight adhesion of the auxiliary film more than if the auxiliary film is deposited directly on a surface of the interlayer insulating film.
    Type: Application
    Filed: November 30, 2005
    Publication date: March 1, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Hideki Kitada, Nobuyuki Ohtsuka, Noriyoshi Shimizu, Yoshiyuki Nakao
  • Publication number: 20070048931
    Abstract: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.
    Type: Application
    Filed: December 28, 2005
    Publication date: March 1, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Noriyoshi Shimizu, Nobuyuki Ohtsuka, Hideki Kitada, Yoshiyuki Nakao
  • Patent number: 6992005
    Abstract: A semiconductor device having a multi-layered wiring structure containing a copper layer, comprises a first insulating film formed over a semiconductor substrate, a first copper pattern buried in the first insulating film, a cap layer formed on the first copper pattern and the first insulating film and made of a substance a portion of which formed on the first copper pattern has a smaller electrical resistance value than a portion formed on the first insulating film, second insulating films formed on the cap layer, and a second copper pattern buried in a hole or a trench, which is formed in the second insulating films on the first copper pattern; and connected electrically to the first copper pattern via the cap layer.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: January 31, 2006
    Assignee: Fujitsu Limited
    Inventors: Nobuyuki Ohtsuka, Noriyoshi Shimizu, Hisaya Sakai, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki
  • Publication number: 20050121786
    Abstract: A semiconductor device comprises a semiconductor substrate and an interlayer interconnection structure provided on the semiconductor substrate. The interlayer interconnection structure includes a porous insulation film and a conductive part of a conductive material containing a metal as a major component. A volume occupation ratio of pores of a diameter greater than 0.6 nanometers is less than 30% in the porous insulation film.
    Type: Application
    Filed: November 3, 2004
    Publication date: June 9, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Akira Furuya, Nobuyuki Ohtsuka, Shinichi Ogawa, Hiroshi Okamura
  • Patent number: 6900542
    Abstract: A semiconductor device comprises of an insulating film (14) formed over a semiconductor substrate (1), a trench (14b) and a hole (14a) formed in the insulating film (14), a first underlying layer (16) formed in at least one of the trench (14b) and the hole (14a) and made of conductive material to prevent diffusion of copper, a main conductive layer (19) formed in at least one of the trench (14b) and the hole (14a) on the first underlying layer (19) and made of copper or copper alloy, and a second underlying layer (17) formed between the main conductive layer (19) and the first underlying layer (16) and having a metal element that is solid-solved in the main conductive layer at an interface between the second underlying layer (17) and the main conductive layer (19), and formed on the first underlying layer (16) by a CVD method.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: May 31, 2005
    Assignee: Fujitsu Limited
    Inventors: Hisaya Sakai, Noriyoshi Shimizu, Nobuyuki Ohtsuka
  • Publication number: 20040259381
    Abstract: In a method for manufacturing a semiconductor device, an insulating film having pores is formed on a substrate, and an opening is formed in the insulating film. Thereafter, a material gas supplying Si or C is supplied to the insulating film. Thereby, deficient elements, such as Si or C, are supplied to the insulating film. Thereafter, in the opening, including a barrier metal, is filled with a conductive member to form a wiring structure.
    Type: Application
    Filed: June 16, 2004
    Publication date: December 23, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Nobuyuki Ohtsuka, Akira Furuya, Shinichi Ogawa, Hiroshi Okamura
  • Publication number: 20040188839
    Abstract: A semiconductor device having a multi-layered wiring structure containing a copper layer, comprises a first insulating film formed over a semiconductor substrate, a first copper pattern buried in the first insulating film, a cap layer formed on the first copper pattern and the first insulating film and made of a substance a portion of which formed on the first copper pattern has a smaller electrical resistance value than a portion formed on the first insulating film, second insulating films formed on the cap layer, and a second copper pattern buried in a hole or a trench, which is formed in the second insulating films on the first copper pattern; and connected electrically to the first copper pattern via the cap layer.
    Type: Application
    Filed: April 7, 2004
    Publication date: September 30, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Nobuyuki Ohtsuka, Noriyoshi Shimizu, Hisaya Sakai, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki