Abstract: A semiconductor arrangement is disclosed. The semiconductor arrangement includes: a semiconductor body and a temperature sensor (TES) integrated in the semiconductor body. The TES includes: a first semiconductor region of a first doping type arranged, in a vertical direction of the semiconductor body, between a second semiconductor region of a second doping type and a third semiconductor of the second doping type, and a contact plug ohmically connecting the first semiconductor region and the second semiconductor region. The first semiconductor region includes a base region section spaced apart from the contact plug in a first lateral direction of the semiconductor body and a resistor section arranged between the base region section and the contact plug. The resistor section is implemented such that an ohmic resistance of the resistor section between the base region section and the first semiconductor region is at least 1 M?.

Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.

Abstract: A semiconductor device includes at least one wiring layer disposed on a semiconductor body, a field effect transistor integrated in the semiconductor body, the field effect transistor having a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body, a first circuit integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit integrated in the semiconductor body and remote from the first circuit. The semiconductor device further includes a first additional trench formed in the semiconductor body and at least one conductive pad formed in the at least one wiring layer. The first additional trench includes at least one connecting line which electrically connects the first circuit and the second circuit. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract: A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in the semiconductor body. The field effect transistor has a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body. A first circuit is integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit is integrated in the semiconductor body remote from the first circuit. A first additional trench is formed in the semiconductor body and includes at least one connecting line which electrically connects the first circuit and the second circuit. The semiconductor device also includes at least one conductive pad formed in the at least one wiring layer. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.

Abstract: An integrated transistor structure includes an epitaxial layer on a semiconductor substrate, a power transistor formed in a first region of the epitaxial layer and having a drain region, a source region and a body region shorted to the source region, a bipolar transistor formed in a second region of the epitaxial layer spaced apart from the power transistor. A first trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the power transistor includes a gate electrode spaced apart from a channel region of the power transistor by an insulating material. A second trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor includes a trench electrode spaced apart from the epitaxial layer by an insulating material. The gate electrode, base and emitter of the bipolar transistor are connected to different contacts isolated from one another.

Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract: A semiconductor component arrangement includes a semiconductor body, a transistor structure, a further component, and at least a first electrode structure. The semiconductor body has a first side and a second side. The transistor structure is integrated in the semiconductor body, and includes a source and a drain. The further component is also integrated in the semiconductor body. The first electrode structure is disposed in at least a first trench, and includes at least one electrode. The first electrode structure electrically connects at least one of the source and the drain to the further component.

Abstract: A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in the semiconductor body. The field effect transistor has a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body. A first circuit is integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit is integrated in the semiconductor body remote from the first circuit. A first additional trench is formed in the semiconductor body and includes at least one connecting line which electrically connects the first circuit and the second circuit. The semiconductor device also includes at least one conductive pad formed in the at least one wiring layer. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.

Abstract: An integrated transistor structure includes an epitaxial layer on a semiconductor substrate, a power transistor formed in a first region of the epitaxial layer and having a drain region, a source region and a body region shorted to the source region, a bipolar transistor formed in a second region of the epitaxial layer spaced apart from the power transistor. A first trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the power transistor includes a gate electrode spaced apart from a channel region of the power transistor by an insulating material. A second trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor includes a trench electrode spaced apart from the epitaxial layer by an insulating material. The gate electrode, base and emitter of the bipolar transistor are connected to different contacts isolated from one another.

Abstract: A semiconductor having an optimized insulation structure which is simple and inexpensive to produce and can be made smaller than LOCOS insulation structures is disclosed. An implantation mask on a surface of a semiconductor substrate is used to implant elements into the semiconductor substrate, which elements, on thermal activation, form an insulation region together with the further elements of the semiconductor substrate. The thermal activation is effected by means of laser irradiation, during which the semiconductor substrate is briefly melted and then recrystallizes during the subsequent cooling, so that the implanted elements form the insulation region together with the further elements of the semiconductor substrate.

Abstract: A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate.

Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.

Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.

Abstract: One embodiment of the invention relates to a field effect trench transistor with a multiplicity of transistor cells that are arranged like an array and whose gate electrodes are arranged in active trenches formed in a semiconductor body. Inactive trenches are arranged in the array of the transistor cells, there being no gate electrodes situated in said inactive trenches, and a series of polysilicon diodes are integrated in one or more of the inactive trenches which diodes, for protection against damage to the gate oxide through ESD pulses, are contact-connected to a source metallization at one of their ends and to a gate metallization at their other end, and/or alternatively or additionally one or more polysilicon zener diodes connected in series is or are integrated in the inactive trench or trenches and contact-connected to the gate metallization by one of its or their ends and to drain potential by its or their other end.