Patents by Inventor Norbert Krischke

Norbert Krischke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9941276
    Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 10, 2018
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Norbert Krischke
  • Publication number: 20170309739
    Abstract: A semiconductor device includes at least one wiring layer disposed on a semiconductor body, a field effect transistor integrated in the semiconductor body, the field effect transistor having a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body, a first circuit integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit integrated in the semiconductor body and remote from the first circuit. The semiconductor device further includes a first additional trench formed in the semiconductor body and at least one conductive pad formed in the at least one wiring layer. The first additional trench includes at least one connecting line which electrically connects the first circuit and the second circuit. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.
    Type: Application
    Filed: July 11, 2017
    Publication date: October 26, 2017
    Inventors: Norbert Krischke, Bernhard Auer, Robert Illing
  • Patent number: 9761665
    Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: September 12, 2017
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Stefan Decker, Norbert Krischke, Christoph Kadow
  • Patent number: 9735264
    Abstract: A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in the semiconductor body. The field effect transistor has a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body. A first circuit is integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit is integrated in the semiconductor body remote from the first circuit. A first additional trench is formed in the semiconductor body and includes at least one connecting line which electrically connects the first circuit and the second circuit. The semiconductor device also includes at least one conductive pad formed in the at least one wiring layer. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: August 15, 2017
    Assignee: Infineon Technologies AG
    Inventors: Norbert Krischke, Bernhard Auer, Robert Illing
  • Patent number: 9590091
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: March 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Adrian Finney, Paolo Del Croce, Luca Petruzzi, Norbert Krischke
  • Patent number: 9564425
    Abstract: An integrated transistor structure includes an epitaxial layer on a semiconductor substrate, a power transistor formed in a first region of the epitaxial layer and having a drain region, a source region and a body region shorted to the source region, a bipolar transistor formed in a second region of the epitaxial layer spaced apart from the power transistor. A first trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the power transistor includes a gate electrode spaced apart from a channel region of the power transistor by an insulating material. A second trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor includes a trench electrode spaced apart from the epitaxial layer by an insulating material. The gate electrode, base and emitter of the bipolar transistor are connected to different contacts isolated from one another.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: February 7, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Christoph Kadow, Thorsten Meyer, Norbert Krischke
  • Publication number: 20160307889
    Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.
    Type: Application
    Filed: June 30, 2016
    Publication date: October 20, 2016
    Inventors: Markus Zundel, Franz Hirler, Norbert Krischke
  • Publication number: 20160260803
    Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.
    Type: Application
    Filed: May 18, 2016
    Publication date: September 8, 2016
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Meyer, Stefan Decker, Norbert Krischke, Christoph Kadow
  • Patent number: 9397091
    Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: July 19, 2016
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Norbert Krischke
  • Patent number: 9355909
    Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 31, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Stefan Decker, Norbert Krischke, Christoph Kadow
  • Patent number: 9299834
    Abstract: A semiconductor component arrangement includes a semiconductor body, a transistor structure, a further component, and at least a first electrode structure. The semiconductor body has a first side and a second side. The transistor structure is integrated in the semiconductor body, and includes a source and a drain. The further component is also integrated in the semiconductor body. The first electrode structure is disposed in at least a first trench, and includes at least one electrode. The first electrode structure electrically connects at least one of the source and the drain to the further component.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 29, 2016
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Norbert Krischke
  • Publication number: 20160071972
    Abstract: A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in the semiconductor body. The field effect transistor has a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body. A first circuit is integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit is integrated in the semiconductor body remote from the first circuit. A first additional trench is formed in the semiconductor body and includes at least one connecting line which electrically connects the first circuit and the second circuit. The semiconductor device also includes at least one conductive pad formed in the at least one wiring layer. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 10, 2016
    Inventors: Norbert Krischke, Bernhard Auer, Robert Illing
  • Publication number: 20160056280
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 25, 2016
    Inventors: Adrian Finney, Paolo Del Croce, Luca Petruzzi, Norbert Krischke
  • Publication number: 20150311195
    Abstract: An integrated transistor structure includes an epitaxial layer on a semiconductor substrate, a power transistor formed in a first region of the epitaxial layer and having a drain region, a source region and a body region shorted to the source region, a bipolar transistor formed in a second region of the epitaxial layer spaced apart from the power transistor. A first trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the power transistor includes a gate electrode spaced apart from a channel region of the power transistor by an insulating material. A second trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor includes a trench electrode spaced apart from the epitaxial layer by an insulating material. The gate electrode, base and emitter of the bipolar transistor are connected to different contacts isolated from one another.
    Type: Application
    Filed: July 6, 2015
    Publication date: October 29, 2015
    Inventors: Christoph Kadow, Thorsten Meyer, Norbert Krischke
  • Patent number: 9142447
    Abstract: A semiconductor having an optimized insulation structure which is simple and inexpensive to produce and can be made smaller than LOCOS insulation structures is disclosed. An implantation mask on a surface of a semiconductor substrate is used to implant elements into the semiconductor substrate, which elements, on thermal activation, form an insulation region together with the further elements of the semiconductor substrate. The thermal activation is effected by means of laser irradiation, during which the semiconductor substrate is briefly melted and then recrystallizes during the subsequent cooling, so that the implanted elements form the insulation region together with the further elements of the semiconductor substrate.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: September 22, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Norbert Krischke
  • Patent number: 9112021
    Abstract: A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 18, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Christoph Kadow, Thorsten Meyer, Norbert Krischke
  • Publication number: 20150008498
    Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.
    Type: Application
    Filed: July 14, 2014
    Publication date: January 8, 2015
    Inventors: Markus Zundel, Franz Hirler, Norbert Krischke
  • Patent number: 8779506
    Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Norbert Krischke
  • Patent number: 8772861
    Abstract: One embodiment of the invention relates to a field effect trench transistor with a multiplicity of transistor cells that are arranged like an array and whose gate electrodes are arranged in active trenches formed in a semiconductor body. Inactive trenches are arranged in the array of the transistor cells, there being no gate electrodes situated in said inactive trenches, and a series of polysilicon diodes are integrated in one or more of the inactive trenches which diodes, for protection against damage to the gate oxide through ESD pulses, are contact-connected to a source metallization at one of their ends and to a gate metallization at their other end, and/or alternatively or additionally one or more polysilicon zener diodes connected in series is or are integrated in the inactive trench or trenches and contact-connected to the gate metallization by one of its or their ends and to drain potential by its or their other end.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Norbert Krischke, Thorsten Meyer
  • Publication number: 20140167155
    Abstract: A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a first side, at least one gate electrode arranged in the trench and insulated from the semiconductor body by a gate dielectric, and at least one source zone and at least one drain zone of a first conduction type, which are formed in the semiconductor body in a manner adjacent to the gate dielectric and in a manner spaced apart from one another in a peripheral direction of the trench and between which at least one body zone of a second conduction type is arranged.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 19, 2014
    Applicant: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Norbert Krischke