Abstract: A programmable activate-precharge cycle are provided for a DRAM device. Activate and precharge signals associated with the activate-precharge cycle are generated on the basis of the programmed rate and precharge time with respect to an internal clock of the DRAM device. The activate and precharge signals are coupled to wordlines of the DRAM device, and switched from one wordline to another under internal or external control. One or more functions of the DRAM device are tested while the activate and precharge signals are coupled to wordline. The manner in which switching the activate and precharge signals from one wordline to another wordline is configured depending on the type of testing to be conducted.

Abstract: A random access memory including an array of memory cells configured to store memory cell data, a first circuit, and a second circuit. The first circuit is configured to compare test data and memory cell data to obtain comparison results. The second circuit is configured to compress the comparison results and store the compressed comparison results.

Abstract: A memory device and methods to exploit extra or dummy wordlines in the memory device, wherein the extra wordlines are not part of a main memory area of the memory device but, when activated, connect their attached memory cells to the bitlines of the main memory area. The extra wordlines are connected to a voltage in such a manner so as to simulate a floating wordline condition. Associated with each extra wordline is a driver circuit that connects the extra wordline to a voltage to allow it to charge up to the voltage, and subsequently disconnects the wordline from the voltage to allow it to float. While the extra wordline is floating, measurements may be made on the memory device to gather data useful for testing production memory chips for floating wordline conditions. According to another aspect, one or more extra wordlines may be activated to connect its attached memory cells to bitlines, thereby increasing the capacitance on the bitlines.

Abstract: Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals provided by a memory tester may be shared by two or more devices under test. A chip selector may be used to select at least one or all the devices sharing a given set of test signals. By sharing test signals between multiple devices, the level of parallel testing may be increased without increasing the pin count and complexity of memory testers and probe cards.

Abstract: A random access memory including first memory cells, second memory cells, a first voltage source, and a second voltage source. The first voltage source is configured to control the first memory cells. The second voltage source is configured to control the second memory cells. Also, the first voltage source is configured to be trimmed independently of the second voltage source to provide a first voltage that reduces leakage from the first memory cells and the second voltage source is configured to be trimmed independently of the first voltage source to provide a second voltage that reduces leakage from the second memory cells.

Abstract: A method and apparatus according to the present invention enable wafer chips to be configured with a single power on and off sequence and further enable a chip parameter to be adjusted during a wafer test without utilizing that sequence. In particular, each wafer chip under test is assigned a unique programmable identification. Once each chip has been assigned a corresponding identification, the chips may each be individually accessible by that identification to provide parameter values to chip registers to configure that chip. The configured chips may be subsequently tested in parallel to evaluate the parameter settings. In addition, the present invention enables chips to share data I/O pins or lines, thereby reducing the quantity of testing machine pins utilized for each chip and enabling a greater quantity of chips to be tested in a parallel fashion.

Abstract: Embodiments of the invention generally provide a method for accessing a local wordline in a segmented memory. In one embodiment, the method includes, during an access to the local wordline, applying a first voltage to the local wordline via a local wordline driver located at a first end of the local wordline. After the access is completed, a second voltage is applied to the local wordline, wherein the second voltage is applied to the local wordline via a pull-down circuit located at a second end of the local wordline opposite from the first end, and wherein one or more memory cells are attached to local wordline between the local wordline driver and the wordline pull-down circuit.

Abstract: Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals provided by a memory tester may be shared by two or more devices under test. A chip selector may be used to select at least one or all the devices sharing a given set of test signals. By sharing test signals between multiple devices, the level of parallel testing may be increased without increasing the pin count and complexity of memory testers and probe cards.

Abstract: A random access memory including an array of memory cells configured to store memory cell data, a first circuit, and a second circuit. The first circuit is configured to compare test data and memory cell data to obtain comparison results. The second circuit is configured to compress the comparison results and store the compressed comparison results.

Abstract: A random access memory including first memory cells, second memory cells, a first voltage source, and a second voltage source. The first voltage source is configured to control the first memory cells. The second voltage source is configured to control the second memory cells. Also, the first voltage source is configured to be trimmed independently of the second voltage source to provide a first voltage that reduces leakage from the first memory cells and the second voltage source is configured to be trimmed independently of the first voltage source to provide a second voltage that reduces leakage from the second memory cells.

Abstract: Devices and methods that allow floating word lines in memory arrays to be detected are provided. By driving local word lines from each side with divided drive lines, local word lines on one side of the memory array may be set to an predetermined voltage level (e.g., an intermediate voltage level between VPP and VNWLL). After disconnecting the local word lines on the one side, memory cells on the other side may be tested for read failures, which may indicate floating word lines on the one side.

Abstract: A method and apparatus according to the present invention enable wafer chips to be configured with a single power on and off sequence and further enable a chip parameter to be adjusted during a wafer test without utilizing that sequence. In particular, each wafer chip under test is assigned a unique programmable identification. Once each chip has been assigned a corresponding identification, the chips may each be individually accessible by that identification to provide parameter values to chip registers to configure that chip. The configured chips may be subsequently tested in parallel to evaluate the parameter settings. In addition, the present invention enables chips to share data I/O pins or lines, thereby reducing the quantity of testing machine pins utilized for each chip and enabling a greater quantity of chips to be tested in a parallel fashion.

Abstract: A programmable activate-precharge cycle are provided for a DRAM device. Activate and precharge signals associated with the activate-precharge cycle are generated on the basis of the programmed rate and precharge time with respect to an internal clock of the DRAM device. The activate and precharge signals are coupled to wordlines of the DRAM device, and switched from one wordline to another under internal or external control. One or more functions of the DRAM device are tested while the activate and precharge signals are coupled to wordline. The manner in which switching the activate and precharge signals from one wordline to another wordline is configured depending on the type of testing to be conducted.

Abstract: Devices and methods that allow floating word lines in memory arrays to be detected are provided. By driving local word lines from each side with divided drive lines, local word lines on one side of the memory array may be set to an predetermined voltage level (e.g., an intermediate voltage level between VPP and VNWLL). After disconnecting the local word lines on the one side, memory cells on the other side may be tested for read failures, which may indicate floating word lines on the one side.

Abstract: A memory device and methods to exploit extra or dummy wordlines in the memory device, wherein the extra wordlines are not part of a main memory area of the memory device but, when activated, connect their attached memory cells to the bitlines of the main memory area. The extra wordlines are connected to a voltage in such a manner so as to simulate a floating wordline condition. Associated with each extra wordline is a driver circuit that connects the extra wordline to a voltage to allow it to charge up to the voltage, and subsequently disconnects the wordline from the voltage to allow it to float. While the extra wordline is floating, measurements may be made on the memory device to gather data useful for testing production memory chips for floating wordline conditions. According to another aspect, one or more extra wordlines may be activated to connect its attached memory cells to bitlines, thereby increasing the capacitance on the bitlines.

Abstract: A memory device and methods to exploit extra or dummy wordlines in the memory device, wherein the extra wordlines are not part of a main memory area of the memory device but, when activated, connect their attached memory cells to the bitlines of the main memory area. The extra wordlines are connected to a voltage in such a manner so as to simulate a floating wordline condition. Associated with each extra wordline is a driver circuit that connects the extra wordline to a voltage to allow it to charge up to the voltage, and subsequently disconnects the wordline from the voltage to allow it to float. While the extra wordline is floating, measurements may be made on the memory device to gather data useful for testing production memory chips for floating wordline conditions. According to another aspect, one or more extra wordlines may be activated to connect its attached memory cells to bitlines, thereby increasing the capacitance on the bitlines.

Abstract: A memory device and methods to exploit extra or dummy wordlines in the memory device, wherein the extra wordlines are not part of a main memory area of the memory device but, when activated, connect their attached memory cells to the bitlines of the main memory area. The extra wordlines are connected to a voltage in such a manner so as to simulate a floating wordline condition. Associated with each extra wordline is a driver circuit that connects the extra wordline to a voltage to allow it to charge up to the voltage, and subsequently disconnects the wordline from the voltage to allow it to float. While the extra wordline is floating, measurements may be made on the memory device to gather data useful for testing production memory chips for floating wordline conditions. According to another aspect, one or more extra wordlines may be activated to connect its attached memory cells to bitlines, thereby increasing the capacitance on the bitlines.

Abstract: A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.

Abstract: A system for limiting the rotational speed of a turbocharger is disclosed. The turbocharger includes a compressor having an outlet fluidly coupled to an intake manifold of an internal combustion engine and a compressor outlet, a turbine having an inlet fluidly coupled to an exhaust manifold of the engine and an outlet. A control computer is configured to compute a maximum compressor outlet pressure value as a function of the compressor inlet pressure, the compressor inlet temperature, an operating condition other than the compressor inlet pressure or temperature and a maximum allowable turbocharger speed value, and to control a turbine swallowing capacity or efficiency control mechanism in a manner that limits compressor outlet pressure to the maximum compressor outlet pressure value to thereby limit rotational speed of the turbocharger to the maximum turbocharger speed value. The operating condition may be, for example, engine intake air flow rate or engine speed.

Abstract: A system for limiting the rotational speed of a turbocharger is disclosed. The turbocharger includes a compressor having an outlet fluidly coupled to an intake manifold of an internal combustion engine and a compressor outlet, a turbine having an inlet fluidly coupled to an exhaust manifold of the engine and an outlet. A control computer is configured to compute a maximum compressor outlet pressure value as a function of the compressor inlet pressure, the compressor inlet temperature, an operating condition other than the compressor inlet pressure or temperature and a maximum allowable turbocharger speed value, and to control a turbine swallowing capacity or efficiency control mechanism in a manner that limits compressor outlet pressure to the maximum compressor outlet pressure value to thereby limit rotational speed of the turbocharger to the maximum turbocharger speed value. The operating condition may be, for example, engine intake air flow rate or engine speed.