Abstract: According to various embodiments, an electrode may include at least one layer including a chemical compound including aluminum and titanium.

Abstract: According to various embodiments, an electrode may include at least one layer including a chemical compound including aluminum and titanium.

Abstract: According to various embodiments, an electrode may include at least one layer including a chemical compound including aluminum and titanium.

Abstract: Various techniques, methods and devices are disclosed where metal is deposited on a substrate, and stress caused by the metal to the substrate is limited, for example to limit a bending of the wafer.

Abstract: Embodiments relate to a method for making a semiconductor structure, the method comprising: forming a seed layer in direct contact with a dielectric material; forming a masking layer over the seed layer; patterning the masking layer to expose the seed layer; forming a fill layer over the exposed seed layer; and causing the seed layer to react with the dielectric layer to form a barrier layer between the fill layer and the dielectric layer.

Abstract: According to various embodiments, an electrode may include at least one layer including a chemical compound including aluminum and titanium.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line.

Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line.

Abstract: Various techniques, methods and devices are disclosed where metal is deposited on a substrate, and stress caused by the metal to the substrate is limited, for example to limit a bending of the wafer.

Abstract: Detecting arcing events in a DC driven semiconductor tool is a challenging process. Various embodiments comprise dedicated sensor devices capable of detecting arcing events by observing the slope of voltage and/or current of a DC power supply line. Using the incorporated interfaces, the sensor could be connected to a computer system. Besides the detector arrangement the unit also provides a method and a corresponding computer program product. Furthermore a simple detection, the unit has the capability of separating the events into its severeness.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line.

Abstract: Embodiments relate to a method for making a semiconductor structure, the method comprising: forming a seed layer in direct contact with a dielectric material; forming a masking layer over the seed layer; patterning the masking layer to expose the seed layer; forming a fill layer over the exposed seed layer; and causing the seed layer to react with the dielectric layer to form a barrier layer between the fill layer and the dielectric layer

Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.

Abstract: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.

Abstract: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.

Abstract: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.

Abstract: A method makes contact with a doping region formed at a substrate surface of a substrate. An insulating layer is applied on the substrate surface and a contact hole is formed in the insulating layer. A metal-containing layer is subsequently deposited on the insulating layer and the surface region of the doping region that is uncovered by the contact hole. In a subsequent thermal process having two steps, first the metal-containing layer is reacted with the silicon of the doping region to form a metal silicide layer and then the rest of the metal-containing layer is converted into a metal-nitride-containing layer in a second thermal step.

Abstract: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.

Abstract: A contact layer is used, for example, as a liner for the fabrication of electrical contacts in contact holes. The contact layer is fabricated in two steps, in a first step a first contact layer is deposited, in which only a small proportion of the particles to be sputtered is ionized. In a second sputtering step, a second contact layer is sputtered, in the course of whose fabrication a larger proportion of the particles to be sputtered is ionized. The procedure ensures that the first contact layer is disposed as a protective layer on the substrate by gentle sputtering before the second contact layer is sputtered.