Patents by Inventor Norbert Werner

Norbert Werner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110073041
    Abstract: In a method for producing epitaxially coated semiconductor wafers, a multiplicity of prepared, front side-polished semiconductor wafers are successively coated individually with an epitaxial layer on their polished front sides at temperatures of 800-1200° C. in a reactor, while supporting the prepared semiconductor wafer over a susceptor having a gas-permeable structure, on a ring placed on the susceptor which acts as a thermal buffer between the susceptor and the supported semiconductor wafer, the semiconductor wafer resting on the ring, and its backside facing but not contacting the susceptor, so that gaseous substances are delivered from a region over the backside of the semiconductor wafer by gas diffusion through the susceptor into a region over the backside of the susceptor, the semiconductor wafer contacting the ring only in an edge region of its backside, wherein no stresses measurable by means of photoelastic stress measurement (“SIRD”) occur in the semiconductor wafer.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 31, 2011
    Applicant: SILTRONIC AG
    Inventors: Reinhard Schauer, Norbert Werner
  • Patent number: 7838398
    Abstract: In a method for producing epitaxially coated semiconductor wafers, a multiplicity of prepared, front side-polished semiconductor wafers are successively coated individually with an epitaxial layer on their polished front sides at temperatures of 800-1200° C. in a reactor, while supporting the prepared semiconductor wafer over a susceptor having a gas-permeable structure, on a ring placed on the susceptor which acts as a thermal buffer between the susceptor and the supported semiconductor wafer, the semiconductor wafer resting on the ring, and its backside facing but not contacting the susceptor, so that gaseous substances are delivered from a region over the backside of the semiconductor wafer by gas diffusion through the susceptor into a region over the backside of the susceptor, the semiconductor wafer contacting the ring only in an edge region of its backside, wherein no stresses measurable by means of photoelastic stress measurement (“SIRD”) occur in the semiconductor wafer.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: November 23, 2010
    Assignee: Siltronic AG
    Inventors: Reinhard Schauer, Norbert Werner
  • Publication number: 20090261456
    Abstract: A multiplicity of silicon wafers polished at least on their front sides are provided and successively coated individually in an epitaxy reactor by a procedure whereby one of the wafers is placed on a susceptor in the epitaxy reactor, is pretreated under a hydrogen atmosphere at a first hydrogen flow rate, and with addition of an etching medium to the hydrogen atmosphere at a reduced hydrogen flow rate in a second step, is subsequently coated epitaxially on its polished front side, and removed from the reactor. An etching treatment of the susceptor follows a specific number of epitaxial coatings. Silicon wafers produced thereby have a global flatness value GBIR of 0.07-0.3 ?m relative to an edge exclusion of 2 mm.
    Type: Application
    Filed: June 29, 2009
    Publication date: October 22, 2009
    Applicant: SILTRONIC AG
    Inventors: Reinhard Schauer, Norbert Werner
  • Patent number: 7579261
    Abstract: A multiplicity of silicon wafers polished at least on their front sides are provided and successively coated individually in an epitaxy reactor by a procedure whereby one of the wafers is placed on a susceptor in the epitaxy reactor, is pretreated under a hydrogen atmosphere at a first hydrogen flow rate, and with addition of an etching medium to the hydrogen atmosphere at a reduced hydrogen flow rate in a second step, is subsequently coated epitaxially on its polished front side, and removed from the reactor. An etching treatment of the susceptor follows a specific number of epitaxial coatings. Silicon wafers produced thereby have a global flatness value GBIR of 0.07-0.3 ?m relative to an edge exclusion of 2 mm.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: August 25, 2009
    Assignee: Siltronic AG
    Inventors: Reinhard Schauer, Norbert Werner
  • Publication number: 20080118712
    Abstract: In a method for producing epitaxially coated semiconductor wafers, a multiplicity of prepared, front side-polished semiconductor wafers are successively coated individually with an epitaxial layer on their polished front sides at temperatures of 800-1200° C. in a reactor, while supporting the prepared semiconductor wafer over a susceptor having a gas-permeable structure, on a ring placed on the susceptor which acts as a thermal buffer between the susceptor and the supported semiconductor wafer, the semiconductor wafer resting on the ring, and its backside facing but not contacting the susceptor, so that gaseous substances are delivered from a region over the backside of the semiconductor wafer by gas diffusion through the susceptor into a region over the backside of the susceptor, the semiconductor wafer contacting the ring only in an edge region of its backside, wherein no stresses measurable by means of photoelastic stress measurement (“SIRD”) occur in the semiconductor wafer.
    Type: Application
    Filed: November 14, 2007
    Publication date: May 22, 2008
    Applicant: Siltronic AG
    Inventors: Reinhard Schauer, Norbert Werner
  • Publication number: 20080053353
    Abstract: A seed box mount is designed to contain four seed boxes yet provide easy access for side loading and unloading of the boxes. The mount can be a trailer, a truck body or a fixed frame. The mount includes an integral seed unloading conveyor which swings from a sidewardly extending unloading position to a stowed position swung forwardly for road transport when used in a trailer embodiment. A rotary platform has receptacle stations for holding each of the four seed boxes and an outlet in each receptacle aligned with the bottom outlet gate of the seed box. Dump chutes including self tending flexible cuffs extend below each of the receptacle stations. The platform rotates under power to selectively position a seed box aligned with the feed end of the conveyor for refilling seed bins of planters, drills and other seeder implements. The seed box mount provides low height, multiple box carrying capacity and because of the design of the dump chute and flexible cuffs, prevents seed spillage.
    Type: Application
    Filed: September 1, 2006
    Publication date: March 6, 2008
    Inventors: Norbert Werner, Thomas A. Klenke, Denny Schawe
  • Patent number: 7285483
    Abstract: A susceptor configured to receive a semiconductor wafer for deposition of a layer on a front surface of the semiconductor wafer by chemical vapor deposition (CVD) has a gas-permeable structure with a porosity of at least 15%, a density of from 0.5 to 1.5 g/cm3, a pore diameter of less than 0.1 mm and an internal surface area of the pores which is greater than 10,000 cm2/cm3. Semiconductor wafers having front surface coated by chemical vapor deposition (CVD) and a polished or etched back surface, prepared using the gas-permeable susceptor, have a nanotopography of the back surface, expressed as the PV (=peak to valley) height fluctuation, of less than 5 nm, and at the same time the halo of the back surface, expressed as haze, is less than 5 ppm.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: October 23, 2007
    Assignee: Silitronic AG
    Inventors: Reinhard Schauer, Norbert Werner
  • Publication number: 20070066036
    Abstract: A multiplicity of silicon wafers polished at least on their front sides are provided and successively coated individually in an epitaxy reactor by a procedure whereby one of the wafers is placed on a susceptor in the epitaxy reactor, is pretreated under a hydrogen atmosphere at a first hydrogen flow rate, and with addition of an etching medium to the hydrogen atmosphere at a reduced hydrogen flow rate in a second step, is subsequently coated epitaxially on its polished front side, and removed from the reactor. An etching treatment of the susceptor follows a specific number of epitaxial coatings. Silicon wafers produced thereby have a global flatness value GBIR of 0.07-0.3 ?m relative to an edge exclusion of 2 mm.
    Type: Application
    Filed: September 15, 2006
    Publication date: March 22, 2007
    Applicant: Siltronic AG
    Inventors: Reinhard Schauer, Norbert Werner
  • Patent number: 7101794
    Abstract: A susceptor for a semiconductor wafer to be placed on during deposition of a layer on a front surface of the semiconductor wafer by chemical vapor deposition (CVD), has a gas-permeable structure with a porosity of at least 15% and a density of from 0.5 to 1.5 g/cm3. There is also a semiconductor wafer having a back surface and a front surface which has been coated by chemical vapor deposition (CVD) and a polished or etched back surface. The nanotopography of the back surface, expressed as the height fluctuation PV (=peak to valley), is less than 5 nm. There is a process for producing the semiconductor wafer.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: September 5, 2006
    Assignee: Siltronic AG
    Inventors: Reinhard Schauer, Norbert Werner
  • Publication number: 20060079089
    Abstract: A susceptor configured to receive a semiconductor wafer for deposition of a layer on a front surface of the semiconductor wafer by chemical vapor deposition (CVD) has a gas-permeable structure with a porosity of at least 15%, a density of from 0.5 to 1.5 g/cm3, a pore diameter of less than 0.1 mm and an internal surface area of the pores which is greater than 10,000 cm2/cm3. Semiconductor wafers having front surface coated by chemical vapor deposition (CVD) and a polished or etched back surface, prepared using the gas-permeable susceptor, have a nanotopography of the back surface, expressed as the PV (=peak to valley) height fluctuation, of less than 5 nm, and at the same time the halo of the back surface, expressed as haze, is less than 5 ppm.
    Type: Application
    Filed: November 18, 2005
    Publication date: April 13, 2006
    Applicant: Siltronic AG
    Inventors: Reinhard Schauer, Norbert Werner
  • Publication number: 20040266181
    Abstract: A susceptor for a semiconductor wafer to be placed on during deposition of a layer on a front surface of the semiconductor wafer by chemical vapor deposition (CVD), has a gas-permeable structure with a porosity of at least 15% and a density of from 0.5 to 1.5 g/cm3. There is also a semiconductor wafer having a back surface and a front surface which has been coated by chemical vapor deposition (CVD) and a polished or etched back surface. The nanotopography of the back surface, expressed as the height fluctuation PV (=peak to valley), is less than 5 nm. There is a process for producing the semiconductor wafer.
    Type: Application
    Filed: May 26, 2004
    Publication date: December 30, 2004
    Applicant: Siltronic AG
    Inventors: Reinhard Schauer, Norbert Werner