Patents by Inventor Noren Pan

Noren Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120227798
    Abstract: The present application utilizes an oxidation process to fabricating a Group III-V compound semiconductor solar cell device. By the oxidation process, a window layer disposed on a cell unit is oxidized to enhance the efficiency of the solar cell device. The oxidized window has an increased band gap to minimize the surface recombination of electrons and holes. The oxidized window also improves transparency at the wavelengths that were absorbed in the conventional window layer.
    Type: Application
    Filed: May 29, 2012
    Publication date: September 13, 2012
    Applicant: MICROLINK DEVICES, INC.
    Inventors: Noren PAN, Christopher YOUTSEY, David S. MCCALLUM, Victor C. ELARDE, John M. DALLESASSE
  • Publication number: 20120088374
    Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BiFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.
    Type: Application
    Filed: April 5, 2011
    Publication date: April 12, 2012
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Publication number: 20110318866
    Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film compound solar cell before it is separated from the substrate. To separate the thin film compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film compound solar cell.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 29, 2011
    Applicant: MICROLINK DEVICES, INC.
    Inventors: Noren PAN, Glen HILLIER, Duy Phach VU, Rao TATAVARTI, Christopher YOUTSEY, David MCCALLUM, Genevieve MARTIN
  • Patent number: 7994419
    Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: August 9, 2011
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Glen Hillier, Duy Phach Vu, Rao Tatavarti, Christopher Youtsey, David McCallum, Genevieve Martin
  • Publication number: 20110147799
    Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
    Type: Application
    Filed: March 1, 2011
    Publication date: June 23, 2011
    Applicant: MICROLINK DEVICES, INC.
    Inventors: Noren Pan, Andree WIBOWO
  • Patent number: 7923318
    Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: April 12, 2011
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Publication number: 20100237388
    Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 23, 2010
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren PAN, Andree Wibowo
  • Publication number: 20100186822
    Abstract: The present application utilizes an oxidation process to fabricating a Group III-V compound semiconductor solar cell device. By the oxidation process, a window layer disposed on a cell unit is oxidized to enhance the efficiency of the solar cell device. The oxidized window has an increased band gap to minimize the surface recombination of electrons and holes. The oxidized window also improves transparency at the wavelengths that were absorbed in the conventional window layer.
    Type: Application
    Filed: January 28, 2010
    Publication date: July 29, 2010
    Applicant: MICROLINK DEVICES, INC.
    Inventors: Noren PAN, Christopher YOUTSEY, David S. MCCALLUM, Victor C. ELARDE, John M. DALLESASSE
  • Patent number: 7687886
    Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: March 30, 2010
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Publication number: 20090044860
    Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.
    Type: Application
    Filed: July 3, 2008
    Publication date: February 19, 2009
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren Pan, Glen Hillier, Duy Phach Vu, Rao Tatavarti, Christopher Youtsey, David McCallum
  • Publication number: 20090038678
    Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.
    Type: Application
    Filed: July 3, 2008
    Publication date: February 12, 2009
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren Pan, Glen Hillier, Duy Phach Vu, Rao Tatavarti, Christopher Youtsey, David McCallum
  • Publication number: 20080230806
    Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.
    Type: Application
    Filed: February 7, 2008
    Publication date: September 25, 2008
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Patent number: 7345327
    Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III-V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: March 18, 2008
    Assignee: Kopin Corporation
    Inventors: Roger E. Welser, Paul M. DeLuca, Charles R. Lutz, Kevin S. Stevens, Noren Pan
  • Patent number: 7186624
    Abstract: A semiconductor material which has a high carbon dopant concentration and is composed of gallium, indium, arsenic and nitrogen is disclosed. The material is useful in forming the base layer of gallium arsenide based heterojunction bipolar transistors because it can be lattice matched to gallium arsenide by controlling the concentration of indium and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentration obtained.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: March 6, 2007
    Assignee: Kopin Corporation
    Inventors: Roger E. Welser, Paul M. Deluca, Noren Pan
  • Patent number: 7115466
    Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III–V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: October 3, 2006
    Assignee: Kopin Corporation
    Inventors: Roger E. Welser, Paul M. Deluca, Charles R. Lutz, Kevin S. Stevens, Noren Pan
  • Publication number: 20060049485
    Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
    Type: Application
    Filed: June 14, 2005
    Publication date: March 9, 2006
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Publication number: 20050158942
    Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III-V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.
    Type: Application
    Filed: January 20, 2005
    Publication date: July 21, 2005
    Applicant: Kopin Corporation
    Inventors: Roger Welser, Paul Deluca, Charles Lutz, Kevin Stevens, Noren Pan
  • Patent number: 6917061
    Abstract: A heterojunction bipolar transistor is provided that has a reduced turn-on voltage threshold. A base spacer layer is provided and alternately an emitter layer is provided that has a lowered energy gap. The lowered energy gap of the base spacer or the emitter spacer allow the heterojunction bipolar transistor to realize a lower turn-on voltage threshold. The thickness of the emitter layer if utilized is kept to a minimum to reduce the associated space charge recombination current in the heterojunction bipolar transistor.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: July 12, 2005
    Assignee: Microlink Devices, Inc.
    Inventors: Noren Pan, Byung-Kwon Han
  • Publication number: 20050139863
    Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III-V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.
    Type: Application
    Filed: October 20, 2004
    Publication date: June 30, 2005
    Applicant: Kopin Corporation
    Inventors: Roger Welser, Paul DeLuca, Charles Lutz, Kevin Stevens, Noren Pan
  • Publication number: 20050064672
    Abstract: A semiconductor material which has a high carbon dopant concentration and is composed of gallium, indium, arsenic and nitrogen is disclosed. The material is useful in forming the base layer of gallium arsenide based heterojunction bipolar transistors because it can be lattice matched to gallium arsenide by controlling the concentration of indium and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentration obtained.
    Type: Application
    Filed: April 14, 2004
    Publication date: March 24, 2005
    Applicant: Kopin Corporation
    Inventors: Roger Welser, Paul Deluca, Noren Pan