Patents by Inventor Noriaki Kawamoto
Noriaki Kawamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153955Abstract: A semiconductor device is manufactured which includes a SiC epitaxial layer, a plurality of transistor cells that are formed in the SiC epitaxial layer and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode that faces a channel region of the transistor cells in which a channel is formed when the semiconductor device is in an ON state, a gate metal that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode while being physically separated from the gate electrode, and a built-in resistor that is made of polysilicon and that is disposed below the gate metal so as to electrically connect the gate metal and the gate electrode together.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Applicant: ROHM CO., LTD.Inventors: Katsuhisa NAGAO, Noriaki KAWAMOTO
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Patent number: 11908868Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: GrantFiled: May 19, 2022Date of Patent: February 20, 2024Assignee: ROHM CO., LTD.Inventors: Katsuhisa Nagao, Noriaki Kawamoto
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Publication number: 20230245959Abstract: A semiconductor device includes a first die pad having a main surface, a second die pad having a second main surface, a first switching element connected to the first main surface, a second switching element connected to the second main surface, a first connecting member connecting the first main surface electrode of the first switching element to the second die pad, an encapsulation resin encapsulating the first switching element, the second switching element, the first die pad, the second die pad, and the first connecting member, and leads projecting out of one of the resin side surfaces of the encapsulation resin.Type: ApplicationFiled: June 23, 2021Publication date: August 3, 2023Inventors: Kenji HAYASHI, Takumi KANDA, Noriaki KAWAMOTO
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Publication number: 20230154815Abstract: A semiconductor device includes: a switching element including a drain electrode, a gate electrode, and a source electrode; a base supporting the switching element; and a first terminal, a second terminal, a third terminal, and a fourth terminal that each extend in the same direction. The switching element includes a temperature detection diode having a first electrode provided on the element obverse surface. Each of the drain electrode, the gate electrode, and the source electrode is electrically connected to a corresponding one of the first terminal, the second terminal, and the third terminal. The first electrode is electrically connected to the fourth terminal via a first wire.Type: ApplicationFiled: April 27, 2021Publication date: May 18, 2023Inventors: Masaharu NAKANISHI, Noriaki KAWAMOTO
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Publication number: 20220278133Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: ApplicationFiled: May 19, 2022Publication date: September 1, 2022Inventors: Katsuhisa NAGAO, Noriaki KAWAMOTO
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Patent number: 11367738Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: GrantFiled: December 2, 2020Date of Patent: June 21, 2022Assignee: ROHM CO., LTD.Inventors: Katsuhisa Nagao, Noriaki Kawamoto
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Publication number: 20210091117Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: ApplicationFiled: December 2, 2020Publication date: March 25, 2021Inventors: Katsuhisa NAGAO, Noriaki KAWAMOTO
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Patent number: 10886300Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: GrantFiled: August 29, 2019Date of Patent: January 5, 2021Assignee: ROHM CO., LTD.Inventors: Katsuhisa Nagao, Noriaki Kawamoto
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Publication number: 20200321451Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.Type: ApplicationFiled: June 18, 2020Publication date: October 8, 2020Inventors: Keiji OKUMURA, Mineo MIURA, Yuki NAKANO, Noriaki KAWAMOTO, Hidetoshi ABE
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Patent number: 10727318Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.Type: GrantFiled: September 9, 2016Date of Patent: July 28, 2020Assignee: ROHM CO., LTD.Inventors: Keiji Okumura, Mineo Miura, Yuki Nakano, Noriaki Kawamoto, Hidetoshi Abe
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Publication number: 20190386025Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: Katsuhisa NAGAO, Noriaki KAWAMOTO
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Patent number: 10438971Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electron (19) together.Type: GrantFiled: January 30, 2018Date of Patent: October 8, 2019Assignee: ROHM CO., LTD.Inventors: Katsuhisa Nagao, Noriaki Kawamoto
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Publication number: 20180175062Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electron (19) together.Type: ApplicationFiled: January 30, 2018Publication date: June 21, 2018Inventors: Katsuhisa NAGAO, Noriaki KAWAMOTO
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Patent number: 9917102Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside: and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: GrantFiled: November 26, 2014Date of Patent: March 13, 2018Assignee: ROHM CO., LTD.Inventors: Katsuhisa Nagao, Noriaki Kawamoto
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Publication number: 20170092743Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.Type: ApplicationFiled: September 9, 2016Publication date: March 30, 2017Applicant: ROHM CO., LTD.Inventors: Keiji OKUMURA, Mineo MIURA, Yuki NAKANO, Noriaki KAWAMOTO, Hidetoshi ABE
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Publication number: 20160379992Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside: and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (41) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: ApplicationFiled: November 26, 2014Publication date: December 29, 2016Applicant: ROHM CO., LTD.Inventors: Katsuhisa NAGAO, Noriaki KAWAMOTO
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Patent number: 9048103Abstract: A method for producing a semiconductor device (20) is disclosed. The semiconductor device (20) includes: 1) a semiconductor substrate (1, 2), 2) a hetero semiconductor area (3) configured to contact a first main face (1A) of the semiconductor substrate (1, 2) and different from the semiconductor substrate (1, 2) in band gap, 3) a gate electrode (7) contacting, via a gate insulating film (6), a part of a junction part (13) between the hetero semiconductor area (3) and the semiconductor substrate (1, 2), 4) a source electrode (8) configured to connect to the hetero semiconductor area (3), and 5) a drain electrode (9) configured to make an ohmic connection with the semiconductor substrate (1, 2). The method includes the following sequential operations: i) forming the gate insulating film (6); and ii) nitriding the gate insulating film (6).Type: GrantFiled: June 26, 2006Date of Patent: June 2, 2015Assignees: NISSAN MOTOR CO., LTD., ROHM CO., LTD.Inventors: Yoshio Shimoida, Hideaki Tanaka, Tetsuya Hayashi, Masakatsu Hoshi, Shigeharu Yamagami, Noriaki Kawamoto, Takayuki Kitou, Mineo Miura, Takashi Nakamura
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Patent number: 8722497Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).Type: GrantFiled: July 29, 2013Date of Patent: May 13, 2014Assignees: Nissan Motor Co., Ltd., Rohm Co., Ltd.Inventors: Satoshi Tanimoto, Noriaki Kawamoto, Takayuki Kitou, Mineo Miura
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Patent number: 8716087Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).Type: GrantFiled: July 29, 2013Date of Patent: May 6, 2014Assignees: Nissan Motor Co., Ltd., Rohm Co., Ltd.Inventors: Satoshi Tanimoto, Noriaki Kawamoto, Takayuki Kitou, Mineo Miura
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Patent number: 8696814Abstract: A disclosed film deposition apparatus includes a process chamber inside which a reduced pressure space is maintained; a gas supplying portion that supplies a film deposition gas to the process chamber; a substrate holding portion that is made of a material including carbon as a primary constituent and holds a substrate in the process chamber; a coil that is arranged outside the process chamber and inductively heats the substrate holding portion; and a thermal insulation member that covers the substrate holding portion and is arranged to be separated from the process chamber, wherein the reduced pressure space is separated into a film deposition gas supplying space to which the film deposition gas is supplied and a thermal insulation space defined between the substrate holding portion and the process chamber, and wherein a cooling medium is supplied to the thermal insulation space.Type: GrantFiled: November 29, 2007Date of Patent: April 15, 2014Assignees: Tokyo Electron Limited, Rohm Co., Ltd.Inventors: Eisuke Morisaki, Hirokatsu Kobayashi, Jun Yoshikawa, Ikuo Sawada, Tsunenobu Kimoto, Noriaki Kawamoto, Masatoshi Aketa