Abstract: A signal generator generates a first internal signal including frequency f1, a second internal signal including frequency f2, and a third internal signal including frequency f3 twice as high as frequency f2, and selects and delivers one from among a first output signal including frequency f1, a second output signal including frequency f1+f2, and a third output signal including frequency f1+f3, using the first, second, and third internal signals.

Abstract: A protection circuit comprises: at least one shielded line arranged to cover an area to be protected over a semiconductor device, the at least one shielded line having only one route from a start point to an end point; a signal generator for applying a signal to the start point of the shielded line; a counter which starts measurement of time in response to application of the signal to the start point of the shielded line by the signal generator and which ends measurement of the time in response to arrival of the signal at the end point of the shielded line; and a comparator for comparing the time measured by the counter with a reference value to output a fraud detection signal according to a result of the comparison.

Abstract: A protection circuit comprises: at least one shielded line arranged to cover an area to be protected over a semiconductor device, the at least one shielded line having only one route from a start point to an end point; a signal generator for applying a signal to the start point of the shielded line; a counter which starts measurement of time in response to application of the signal to the start point of the shielded line by the signal generator and which ends measurement of the time in response to arrival of the signal at the end point of the shielded line; and a comparator for comparing the time measured by the counter with a reference value to output a fraud detection signal according to a result of the comparison.

Abstract: A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides, wherein: each of the one ends of the plurality of wires is point-symmetric to any of the other ends of the plurality of wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.

Abstract: When the scribe region 2 is cut off, the dicing detector 53 sends the detection signal A to the changeover circuit 51 and electrically shuts off the pad 50 and the inspection objective circuit 52, and the fixed potential of the input and output passage 54 from the changeover circuit 51 to the inspection objective circuit 52 is monitored by the detector 55. At the same time, the detection objective circuit 52 is changed into a mode, in which a reception of the command of the inspection mode is refused, by the detection signal A. In the case where an abnormality of the fixed potential of the input and output passage 54 is grasped, the inspection objective circuit 52 is changed into the safety mode.

Abstract: A data carrier system includes: a first memory, which is a ferroelectric memory; a second memory; a polarization canceling circuit for canceling polarization of the first memory in accordance with an instruction given thereto; and a control circuit for making data access to the first and second memories and controlling operation of the polarization canceling circuit. Upon receipt of a first instruction, the control circuit saves data stored in the first memory to the second memory and then gives an instruction for canceling polarization to the polarization canceling circuit, while upon receipt of a second instruction, the control circuit writes the data saved to the second memory back into the first memory.

Abstract: A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides, wherein: each of the one ends of the plurality of wires is point-symmetric to any of the other ends of the plurality of wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.

Abstract: A PLL circuit comprises a phase comparator for comparing phases between a reference signal and an internal signal and outputting a phase difference signal according to a phase difference therebetween, a voltage controlled oscillator group composed of a plurality of oscillators which have mutually different frequency variable ranges and whose oscillation frequencies are respectively controlled in accordance with a phase control signal, a selecting means for selecting one of the outputs from the plurality of oscillators based on the phase difference signal or the phase control signal, and a frequency divider for generating the internal signal by dividing an output of an oscillator selected by the selecting means, and when the oscillator selecting state is changed, an output phase of the frequency divider is approximated to the phase of the reference signal. Thereby, a required voltage controlled oscillator can be selected in a short time according to a desirable oscillation frequency.

Abstract: The semiconductor device of the present invention includes: first defensive wiring provided above a diffusion isolation layer formed in a substrate or a well, arranged at a minimum wiring pitch allowable in fabrication to cover the diffusion isolation layer; a plurality of signal wiring layers formed above the first defensive wiring; and means for applying a predetermined signal to the first defensive wiring and capturing a change in an electrical or physical property of the first defensive wiring.

Abstract: A base band signal input from an input terminal (10) has a DC component which is blocked off by a high pass filter (12). When the signal which has passed through the high pass filter (12) has a voltage out of a predetermined set voltage range, the signal of the voltage portion out of the voltage range is extracted by a signal extraction circuit (15). According to the signal extracted, the DC potential of the base band signal is adjusted at a feedback point (17).

Abstract: In a bipolar transistor including a base layer made of SiGe, a non-doped SiGe layer and a non-doped Si layer are provided between the base layer and an emitter layer. The composition ratio of Ge in the emitter side of SiGe base layer is decreased with increasing proximity to the emitter side, and the composition ratio of Ge in the non-doped SiGe layer is made smaller than the composition ratio of Ge at the emitter layer-side end of the SiGe base layer. In this manner, restriction is put on the diffusion of boron from the base layer to the emitter side, and the base-emitter junction capacitance CBE reduced. Furthermore, the direct-current gain ? can be improved by increasing the composition of Ge at the emitter end of the SiGe base layer to more than or equal to a predetermined value.

Abstract: A semiconductor integrated circuit device (10) is composed of an LSI function unit (11) and a shield wiring layer (22) formed on the unit. The LSI function unit (11) includes a semiconductor substrate (12) and a first insulating film (13), and the semiconductor substrate (12) is formed with a circuit element including, for example, a MOS transistor (14). The shield wiring layer (22) is composed of a lower shield line (23), a third insulating film (24), an upper shield line (25), and a fourth insulating film (26) sequentially stacked above a second insulating film (17). The directions in which the lower and upper shield lines (23) and (25) are arranged intersect each other.

Abstract: A semiconductor integrated circuit device (10) is composed of an LSI function unit (11) and a shield wiring layer (22) formed on the unit. The LSI function unit (11) includes a semiconductor substrate (12) and a first insulating film (13), and the semiconductor substrate (12) is formed with a circuit element including, for example, a MOS transistor (14). The shield wiring layer (22) is composed of a lower shield line (23), a third insulating film (24), an upper shield line (25), and a fourth insulating film (26) sequentially stacked above a second insulating film (17). The directions in which the lower and upper shield lines (23) and (25) are arranged intersect each other.

Abstract: A PLL circuit comprises a phase comparator for comparing phases between a reference signal and an internal signal and outputting a phase difference signal according to a phase difference therebetween, a voltage controlled oscillator group composed of a plurality of oscillators which have mutually different frequency variable ranges and whose oscillation frequencies are respectively controlled in accordance with a phase control signal, a selecting means for selecting one of the outputs from the plurality of oscillators based on the phase difference signal or the phase control signal, and a frequency divider for generating the internal signal by dividing an output of an oscillator selected by the selecting means, and when the oscillator selecting state is changed, an output phase of the frequency divider is approximated to the phase of the reference signal. Thereby, a required voltage controlled oscillator can be selected in a short time according to a desirable oscillation frequency.

Abstract: Signal processing apparatus or non-integer divider with a small circuit scale and a fractional N-PLL synthesizer comprising same. An adder 2 and a delay device 4 constitute a 20-bit input accumulator and its input is connected to a signal input terminal 1. Adder 8 and a delay device 10 constitute a 9-bit input accumulator. Into higher 8 bits of its input, higher 8 bits of the output of the accumulator comprising the adder 2 and the delay device 4 are inputted. The output of a 3-input NAND gate 30 is connected to the remaining lowest bit input. An adder 13 and a delay device 15 constitute a 6-bit input accumulator. Higher 6 bits of an output signal of the adder 8 are inputted into this 6-bit input accumulator. An adder 18 and a delay device 20 constitute a 4-bit input accumulator. Higher 4 bits of an output signal of the adder 13 are inputted into this 4-bit input accumulator. Lower 3 bits of output data of the 4-bit delay device 20 are inputted into the 3-input NAND gate 30.

Abstract: A signal input into an input terminal 1 is input into mixers 2, 4, and down-converted with local signals having a phase difference of 90 degrees, respectively, whereby an I-signal and a Q-signal are obtained. An output signal from the mixer 4 is delayed 90 degrees in phase by a phase shifter 6. An adder 7 outputs a sum signal of the I-signal and the Q-signal, and a subtracter 8 outputs a subtracted signal between the I-signal and the Q-signal. The sum signal and the subtracted signal are input into band pass filters 9, 10, in which signals in undesired frequency band are cut, then converted into digital signals by AD converters 11, 12 and input into a signal processor 13. In the signal processor 13, a correlation signal of the sum signal and the subtracted signal is formed, and an image signal included in the sum signal is removed using the correlation signal and the subtracted signal.

Abstract: When the scribe region 2 is cut off, the dicing detector 53 sends the detection signal A to the changeover circuit 51 and electrically shuts off the pad 50 and the inspection objective circuit 52, and the fixed potential of the input and output passage 54 from the changeover circuit 51 to the inspection objective circuit 52 is monitored by the detector 55. At the same time, the detection objective circuit 52 is changed into a mode, in which a reception of the command of the inspection mode is refused, by the detection signal A. In the case where an abnormality of the fixed potential of the input and output passage 54 is grasped, the inspection objective circuit 52 is changed into the safety mode.

Abstract: A protection circuit comprises: at least one shielded line arranged to cover an area to be protected over a semiconductor device, the at least one shielded line having only one route from a start point to an end point; a signal generator for applying a signal to the start point of the shielded line; a counter which starts measurement of time in response to application of the signal to the start point of the shielded line by the signal generator and which ends measurement of the time in response to arrival of the signal at the end point of the shielded line; and a comparator for comparing the time measured by the counter with a reference value to output a fraud detection signal according to a result of the comparison.

Abstract: A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the wires being on one of opposite sides, and the other ends of the wires being on the other one of the opposite sides, wherein: each of the one ends of the wires is point-symmetric to any of the other ends of the wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.

Abstract: A base bias circuit (1) operates like a constant voltage source, and a base bias voltage generated thereby varies according to fluctuation of the environment temperature without being influenced by the supply voltage, to hold a collector bias voltage constant. The base bias circuit (1) has a function of controlling the base bias voltage according to a control signal coming from the outside. By using a resistor (6) and resistor (14) having suitable resistances, the bipolar transistors constituting the bias circuit (1) can be small in size to reduce the electric current consumed by the bias circuit (1) thereby to make unnecessary the RF choke inductor between a power transistor (13) and the bias circuit (1). In short, the cost is lowered by making the chip size small and by reducing the number of external parts.