Patents by Inventor Noriaki Matsuno

Noriaki Matsuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040094823
    Abstract: In a bipolar transistor including a base layer made of SiGe, a non-did SiGe layer and a non-doped Si layer are provided between the base layer and an emitter layer. The composition ratio of Ge in the emitter side of SiGe base layer is decreased with increasing proximity to the emitter side, and the composition ratio of Ge in the non-doped SiGe layer is a smaller than the composition ratio of Ge at the emitter layer-side end of the SiGe base layer. In this manner, restriction is put on the diffusion of boron from the base layer to the emitter side, and the base-emitter junction capacitance CBE reduced. Furthermore, the direct-current gain &bgr; can be improved by increasing the composition of Ge at the emitter end of the SiGe base layer to more than or equal to a predetermined value.
    Type: Application
    Filed: September 5, 2003
    Publication date: May 20, 2004
    Inventor: Noriaki Matsuno
  • Publication number: 20040032700
    Abstract: A base bias circuit (1) operates like a constant voltage source, and a base bias voltage generated thereby varies according to fluctuation of the environment temperature without being influenced by the supply voltage, to hold a collector bias voltage constant. The base bias circuit (1) has a function of controlling the base bias voltage according to a control signal coming from the outside. By using a resistor (6) and resistor (14) having suitable resistances, the bipolar transistors constituting the bias circuit (1) can be small in size to reduce the electric current consumed by the bias circuit (1) thereby to make unnecessary the RF choke inductor between a power transistor (13) and the bias circuit (1). In short, the cost is lowered by making the chip size small and by reducing the number of external parts.
    Type: Application
    Filed: July 9, 2003
    Publication date: February 19, 2004
    Inventors: Noriaki Matsuno, Tomohisa Hirayama
  • Patent number: 6163221
    Abstract: A high-frequency amplification device having an active element and a matching circuit and a bias supplying circuit for the active element, wherein the active element has such a small resistance component of input impedance that gives a stability factor k of less than 1 for the active element itself at a frequency band that the high-frequency amplification device is used, and a loss of the matching circuit or bias supplying circuit or a loss of the matching circuit and bias supplying circuit is used to give a stability factor k of greater than 1 for the high-frequency amplification device.
    Type: Grant
    Filed: April 23, 1999
    Date of Patent: December 19, 2000
    Assignee: NEC Corporation
    Inventor: Noriaki Matsuno
  • Patent number: 6111461
    Abstract: A high frequency amplifier circuit includes the voltage source supplying the power source voltage on the output side of the high frequency amplifying active element. The high frequency amplifier is constructed with a voltage detector detecting a difference frequency voltage of the input signal at a frequency lower than the input signal of the high frequency amplifier circuit and control portion for attenuating the difference frequency voltage from the output signal by controlling the power source voltage on the basis of the difference frequency voltage detected by the voltage detector. Therefore, distortion due to modulating the input signal with the difference frequency component of the input signal can be reduced.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: August 29, 2000
    Assignee: NEC Corporation
    Inventor: Noriaki Matsuno
  • Patent number: 5942943
    Abstract: There is provided an electrical power amplifier device in which an output voltage amplitude is increased without generating any problems such as a reduction of gain, an increasing of loss and providing a large-sized device. The electrical amplifier device of the present invention is operated such that a bias point and a gradient of a load line are set as follows. That is, in the electrical power amplifier device of the present invention, a bias point of a source-grounded field-effect transistor is set to a point where a drain bias current is higher than that of the class A bias point. In addition, in the electrical power amplifier device of the present invention, a gradient of a load line is set to have a relation of a first voltage V.sub.1 >a second voltage V.sub.2. In this case, the first voltage V.sub.1 is a voltage obtained by subtracting a power supply voltage V.sub.dd from a voltage attained at a crossing point between the load line and the voltage axis. In addition, the second voltage V.sub.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: August 24, 1999
    Assignee: NEC Corporation
    Inventor: Noriaki Matsuno
  • Patent number: 5793380
    Abstract: A method for fitting a large number of data points physically obtained to a fitting straight line or fitting curved line defined by fitting parameters and determining the fitting parameters. The method does not need a least square approximation treatment. The method has the steps of (a) assuming a function of an object of fitting in which parameters are included; (b) determining representatives of the parameters and calculating the number of those of the data points which are present in the proximity of a point defined by a group of predetermined variations of the parameters; and (c) varying the representatives to determine those representatives at which the number of the data points exhibit a highest value and determining the representatives then as the fitting parameters.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: August 11, 1998
    Assignee: NEC Corporation
    Inventor: Noriaki Matsuno
  • Patent number: 5723983
    Abstract: A circuit component such as a field effect transistor in a semiconductor device is evaluated without an influence of parasitic components by comparing a set of y-parameters or a set of z-parameters of the circuit component with a set of y-parameters or a set of z-parameters of a first comparative sample equivalent to the semiconductor device without the circuit component and a set of y-parameters or a set of z-parameters of a second comparative sample equivalent to the semiconductor device with the circuit component short-circuited, and the sets of y-parameters or z-parameters are obtained from sets of four-terminal parameters measured under the same conditions.
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: March 3, 1998
    Assignee: NEC Corporation
    Inventor: Noriaki Matsuno
  • Patent number: 5619146
    Abstract: In a switching speed fluctuation detecting apparatus, an input terminal for receiving a signal having a definite time period, a series arrangement of at least one first logic circuit connected to the input terminal, a second logic circuit having a first input connected to the input terminal and a second input connected to an output of the series arrangement and an integrator connected to an output of the second logic circuit are provided.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: April 8, 1997
    Assignee: NEC Corporation
    Inventors: Masahiro Fujii, Yasuo Ohno, Tadashi Maeda, Takao Atsumo, Noriaki Matsuno, Keiichi Numata, Nobuhide Yoshida