Abstract: A semiconductor device comprises a convex portion, a concave portion provided so as to cover upper and side surfaces of the convex portion, a gate electrode provided so as to be opposed to the convex portion with a gate insulating film interposed between the gate electrode and the convex portion, a pair of diffusion layers provided within the convex portion so as to sandwich the gate electrode, and a contact plug provided on the concave portion, so as to be electrically connected to at least one of the diffusion layers.

Abstract: Disclosed herein is a device that includes: a substrate having a gate trench; a gate electrode embedded in the gate trench with an intervention of a gate insulation film; and an embedded insulation film embedded in the gate trench. The substrate includes a first impurity diffusion region in contact with the embedded insulation film and a second impurity diffusion region in contact with the gate insulation film. The gate trench including a first trench portion extending in a first direction and second and third trench portions branching from the first trench portion and extending in a second direction that crosses the first direction. The gate electrode including first, second and third electrode portions embedded in the first, second and third trench portions of the gate trench, respectively. The first impurity diffusion region being sandwiched between the second and third electrode portions.

Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor layer; a first gate insulating film; a floating gate electrode; a second gate insulating film; and a control gate electrode. The semiconductor layer is provided on a substrate and extends in a certain direction. The first gate insulating film is formed on the semiconductor layer. The floating gate electrode is formed along the semiconductor layer on the first gate insulating film. The second gate insulating film is formed on an upper surface of the floating gate electrode. The control gate electrode faces the upper surface of the floating gate electrode via the second gate insulating film. The control gate electrode comprises: a first portion intersecting the certain direction at a first angle; and a second portion intersecting the certain direction at a second angle different from the first angle.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises: a semiconductor substrate; a first gate insulating film; a floating gate electrode; a second gate insulating film; and a control gate electrode. The first gate insulating film is formed on the semiconductor substrate. The floating gate electrode is formed arranged in a first direction on the first gate insulating film. The second gate insulating film is formed on an upper surface and a side surface of the floating gate electrode. The control gate electrode is formed extending in the first direction and facing the upper surface and the side surface of the floating gate electrode via the second gate insulating film. In addition, the floating gate electrode includes boron. Moreover, a concentration of boron in the floating gate electrode is higher with being further from the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.

Abstract: Disclosed herein is a device that includes: first to fourth conductive lines embedded in a semiconductor substrate; a first semiconductor pillar located between the first and second conductive lines; a second semiconductor pillar located between the second and third conductive lines; a third semiconductor pillar located between the third and fourth conductive lines; a first storage element connected to an upper portion of the first semiconductor pillar; a second storage element connected to an upper portion of the third semiconductor pillar; and a bit line embedded in the semiconductor substrate connected to lower portions of the first to third semiconductor pillars. At least one of the first and second conductive lines and at least one of the third and fourth conductive lines being supplied with a potential so as to form channels in the first and third semiconductor pillars.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first groove; and a plurality of first pillars over the substrate. The plurality of first pillars is disposed beside the first groove. A first insulator is disposed in the first groove. A bit contact is disposed in the first groove and over the first insulator. The bit contact is coupled to side surfaces of the plurality of first pillars.

Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.

Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second sides opposite to each other; a first diffusion region underneath the first gate groove; a second diffusion region in the semiconductor substrate, the second diffusion region covering an upper portion of the first side of the first gate groove; and a third diffusion region in the semiconductor substrate. The third diffusion region covers the second side of the first gate groove. The third diffusion region is coupled to the first diffusion region. The third diffusion region has a bottom which is deeper than a bottom of the first gate groove. The bottom of the third diffusion region is different in level from the bottom of the first diffusion region.

Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.

Abstract: Disclosed herein is a device that includes: first to fourth conductive lines embedded in a semiconductor substrate; a first semiconductor pillar located between the first and second conductive lines; a second semiconductor pillar located between the second and third conductive lines; a third semiconductor pillar located between the third and fourth conductive lines; a first storage element connected to an upper portion of the first semiconductor pillar; a second storage element connected to an upper portion of the third semiconductor pillar; and a bit line embedded in the semiconductor substrate connected to lower portions of the first to third semiconductor pillars. At least one of the first and second conductive lines and at least one of the third and fourth conductive lines being supplied with a potential so as to form channels in the first and third semiconductor pillars.

Abstract: A semiconductor device may include, but is not limited to: a semiconductor substrate; a first insulating film; a conductive film; and a semiconductor film. The semiconductor substrate has a first hole. The semiconductor substrate has a first region into which a first impurity is introduced. The first region is adjacent to a side surface of the first hole. The first insulating film covers at least the side surface and a bottom surface of the first hole. The first insulating film has a second hole adjacent to the side surface of the first hole. The conductive film fills a bottom portion of the first hole. The semiconductor film is positioned over the conductive film. The semiconductor film fills the second hole and is in contact with the first region.

Abstract: Disclosed herein is a device that includes: a substrate having a gate trench; a gate electrode embedded in the gate trench with an intervention of a gate insulation film; and an embedded insulation film embedded in the gate trench. The substrate includes a first impurity diffusion region in contact with the embedded insulation film and a second impurity diffusion region in contact with the gate insulation film. The gate trench including a first trench portion extending in a first direction and second and third trench portions branching from the first trench portion and extending in a second direction that crosses the first direction. The gate electrode including first, second and third electrode portions embedded in the first, second and third trench portions of the gate trench, respectively. The first impurity diffusion region being sandwiched between the second and third electrode portions.

Abstract: A semiconductor device includes a first gate trench, a second gate trench, and a dummy gate trench provided in an active region extending in an X direction; and a first gate electrode, a second gate electrode, and a dummy gate electrode extending in a Y direction crossing the active region, at least a part of which are buried in the first gate trench, the second gate trench, and the dummy gate trench, respectively. The dummy gate electrode arranged between second and third diffusion layers isolates and separates a transistor constituted by the first gate electrode and first and second diffusion layers provided on both sides of the first gate electrode, respectively, from a transistor constituted by the second gate electrode and third and fourth diffusion layers provided on both sides of the second gate electrode, respectively.

Abstract: A semiconductor device may include, but is not limited to: a semiconductor substrate; a bit line; and a contact portion. The semiconductor substrate has a first groove having at least first and second side surfaces facing each other. The bit line is positioned in the first groove. The bit line is insulated from the semiconductor substrate. The contact portion is positioned in the first groove. The contact portion is electrically connected to the bit line. The contact portion contacts the first side surface of the first groove. The contact portion is insulated from the second side surface of the first groove.

Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second sides opposite to each other; a first diffusion region underneath the first gate groove; a second diffusion region in the semiconductor substrate, the second diffusion region covering an upper portion of the first side of the first gate groove; and a third diffusion region in the semiconductor substrate. The third diffusion region covers the second side of the first gate groove. The third diffusion region is coupled to the first diffusion region. The third diffusion region has a bottom which is deeper than a bottom of the first gate groove. The bottom of the third diffusion region is different in level from the bottom of the first diffusion region.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first groove; and a plurality of first pillars over the substrate. The plurality of first pillars is disposed beside the first groove. A first insulator is disposed in the first groove. A bit contact is disposed in the first groove and over the first insulator. The bit contact is coupled to side surfaces of the plurality of first pillars.

Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.

Abstract: A semiconductor device includes a semiconductor substrate and a first gate structure. The semiconductor substrate has a first groove and a first pillar defined by the first groove. The first groove and the first pillar are adjacent to each other. The first gate structure is disposed in the first groove. The first gate structure includes a first gate insulating film and a first gate electrode. The first gate structure is separated by a first gap from the first pillar.

Abstract: A semiconductor device includes a first semiconductor pillar, a second semiconductor pillar, and a first wiring. The first semiconductor pillar includes a first diffusion region. The second semiconductor pillar is adjacent to the first semiconductor pillar. The first wiring is positioned between the first and second semiconductor pillars. The first wiring has a first metal surface. The first metal surface has an ohmic contact with the first diffusion region.