Abstract: Apparatuses including a loopback circuit are disclosed. An example apparatus according to the disclosure includes a plurality of input signal receivers and a loopback circuit coupled to the plurality of input signal receivers. The loopback circuit includes a signal multiplexer and a selector. The signal multiplexer provides an input signal received at one input receiver of the plurality of input receivers as a selected signal. The selector coupled to the signal multiplexer provides a loopback signal based on the selected signal and an alleviation signal that transitions between two different states, periodically.

Abstract: An exemplary semiconductor device includes an internal clock circuit configured to intermittently enable and disable a clock signal while in a Maximum Power Savings Mode. The duty cycle of the enablement and disablement of the clock signal may be based on susceptibility to negative-bias temperature instability of a component of the semiconductor device. The clock signal may be enabled and disabled via a synchronizer.

Abstract: A wallet system includes a terminal having a first processor and the first server having a second processor. The first processor is configured to transmit a reloading method registration request to a first server, transmit a reloading request to the first server, and transmit a settlement request to the first server via a terminal of a settlement recipient. The second processor is configured to register a payment method as the reloading method, increase a balance of electronic money in the wallet based on reloading amount information included in the reloading request, and reduce the balance of electronic money in the wallet based on settlement amount information included in the settlement request. The payment method is included in the reloading method registration request.

Abstract: An information processing device according to the present disclosure includes a processor having hardware. The processor extracts an area that a user has passed based on location information of a device that moves with the user, acquires donation information of the extracted area, to create guidance information including the acquired donation information, and displays the guidance information on a user terminal of the user.

Abstract: An information processing apparatus includes a processor having hardware. The processor is configured to create distribution information including a privilege according to an area contribution degree in a visit area at a first distance or more from a residential area of a user based on an activity history of the user and displays the distribution information on a user terminal of the user.

Abstract: An information processing apparatus includes a processor having hardware. The processor is configured to calculate a total score of a borrower who desires to use a lending service, based on a use record score determined by a use record of the borrower in the lending service and a credibility score determined by a payment record of each settlement means, output the total score of the borrower to a terminal of the lender, and output a lending permission and inhibition result to a terminal of the borrower according to response information acquired from the terminal of the lender.

Abstract: A wallet system includes a terminal having a first processor and the first server having a second processor. The first processor is configured to transmit a reloading method registration request to a first server, transmit a reloading request to the first server, and transmit a settlement request to the first server via a terminal of a settlement recipient. The second processor is configured to register a payment method as the reloading method, increase a balance of electronic money in the wallet based on reloading amount information included in the reloading request, and reduce the balance of electronic money in the wallet based on settlement amount information included in the settlement request. The payment method is included in the reloading method registration request.

Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.

Abstract: The present invention is provided with; subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or VKK2 to the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKK1 or VKK2.

Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.

Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.

Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.

Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.

Abstract: Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.

Abstract: The present invention is provided with; subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or VKK2 to the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKK1 or VKK2.

Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.

Abstract: The present invention is provided with: subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or VKK2 to the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKK1 or VKK2.

Abstract: Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.

Abstract: Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.

Abstract: Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers driving the local switch control lines in response to potentials of the main switch control lines, and main switch drivers selectively activating the main switch control lines.